Decoding control with address transition detection in page erase function
First Claim
1. An apparatus for detecting whether a first multi-bit block address portion of a first address is different from a second multi-bit block address portion of a second address in that at least one bit of the first multi-bit block address portion of the first address is different from at least one corresponding bit of the second multi-bit block address portion of the second address, the apparatus comprising:
- for each bit of the first multi-bit block address portion, a respective address detection circuit for detecting whether the bit is different from the corresponding bit of the second multi-bit block address portion; and
a combining circuit for combining outputs of the address detection circuits to produce an output indicative of whether the first multi-bit block address portion of the first address is different from the second multi-bit block address portion of the second address; and
N inputs, where N is the number of bits in the first multi-bit block address portion, and also is the number of bits in the second multi-bit block address portion;
wherein for each input of the N inputs, the apparatus is configured to receive through the input a bit of the first multi-bit block address portion followed by the corresponding bit of the second multi-bit block address portion; and
wherein each address detection circuit comprises;
a rise detecting circuit for detecting rising address transitions;
a fall detecting circuit for detecting falling address transitions; and
a combining circuit for combining outputs of the rise detecting circuit and the fall detecting circuit.
8 Assignments
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Accused Products
Abstract
Circuits and methods are provided for controlling multi-page erase operations in flash memory. The page address of each address of a multi-page erase operation is latched in wordline decoders. A page select reset generator circuit processes the block addresses of each address of the multi-page erase operation. In the event the addresses relate to pages in different blocks, then previously latched page addresses are reset. This avoids the incorrect circuit operation that will result should a multi-page erase operation include multiple pages in different blocks.
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Citations
12 Claims
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1. An apparatus for detecting whether a first multi-bit block address portion of a first address is different from a second multi-bit block address portion of a second address in that at least one bit of the first multi-bit block address portion of the first address is different from at least one corresponding bit of the second multi-bit block address portion of the second address, the apparatus comprising:
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for each bit of the first multi-bit block address portion, a respective address detection circuit for detecting whether the bit is different from the corresponding bit of the second multi-bit block address portion; and a combining circuit for combining outputs of the address detection circuits to produce an output indicative of whether the first multi-bit block address portion of the first address is different from the second multi-bit block address portion of the second address; and N inputs, where N is the number of bits in the first multi-bit block address portion, and also is the number of bits in the second multi-bit block address portion; wherein for each input of the N inputs, the apparatus is configured to receive through the input a bit of the first multi-bit block address portion followed by the corresponding bit of the second multi-bit block address portion; and wherein each address detection circuit comprises; a rise detecting circuit for detecting rising address transitions; a fall detecting circuit for detecting falling address transitions; and a combining circuit for combining outputs of the rise detecting circuit and the fall detecting circuit. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method for detecting whether a first multi-bit block address portion of a first address is different from a second multi-bit block address portion of a second address in the sense that at least one bit of the first multi-bit block address portion of the first address is different from at least one corresponding bit of the second multi-bit block address portion of the second address, the method comprising:
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for each bit of the first multi-bit block address portion, detecting whether the bit is different from the corresponding bit of the second multi-bit block address portion; and combining results of the detecting to produce an output indicative of whether the first multi-bit block address portion of the first address is different from the second multi bit block address portion of the second address; and N is the number of bits in the first multi-bit block address portion, and also is the number of bits in the second multi-bit block address portion; the method further comprising; for each of the N bits of the first multi-bit block address portion, receiving a respective signal comprising the bit of the first multi-bit block address portion followed by the corresponding bit of the second multi-bit block address portion; and wherein for each bit of the multi-bit block address, detecting comprises; detecting rising address transitions; detecting failing address transitions; and combining results of detecting rising address transitions and detecting falling address transitions. - View Dependent Claims (8, 9, 10, 11, 12)
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Specification