Methods and systems for DSP-based receivers
First Claim
1. A method for receiving data signals, comprising:
- (a) receiving a data signal;
(b) generating N sampling signals, each of said N sampling signals having an associated phase;
(c) controlling N analog-to-digital converter (“
ADC”
) paths with said N sampling signals to sample said data signal at said phases;
(d) individually adjusting said N sampling signals to reduce phase errors between said received data signal and each of said N sampling signals in said N ADC paths; and
(e) generating a digital signal representative of said received data signal from samples received from said N ADC paths.
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Accused Products
Abstract
Digital signal processing based methods and systems for receiving data signals include parallel receivers, multi-channel receivers, timing recovery schemes, and, without limitation, equalization schemes. The present invention is implemented as a multi-path parallel receiver in which an analog-to-digital converter (“ADC”) and/or a digital signal processor (“DSP”) are implemented with parallel paths that operate at lower rates than the received data signal. In an embodiment, a parallel DSP-based receiver in accordance with the invention includes a separate timing recovery loop for each ADC path. In an embodiment, a parallel DSP-based receiver includes a separate automatic gain control (AGC) loop for each ADC path. In an embodiment, a parallel DSP-based receiver includes a separate offset compensation loop for each ADC path. In an embodiment, the present invention is implemented as a multi-channel receiver that receives a plurality of data signals.
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Citations
26 Claims
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1. A method for receiving data signals, comprising:
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(a) receiving a data signal; (b) generating N sampling signals, each of said N sampling signals having an associated phase; (c) controlling N analog-to-digital converter (“
ADC”
) paths with said N sampling signals to sample said data signal at said phases;(d) individually adjusting said N sampling signals to reduce phase errors between said received data signal and each of said N sampling signals in said N ADC paths; and (e) generating a digital signal representative of said received data signal from samples received from said N ADC paths. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A receiver, comprising:
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a receiver input; an analog-to-digital converter (“
ADC”
) array of N ADC paths, each of said N ADC paths coupled to said receiver input;an M-path DSP coupled to said ADC array, said M-path DSP having a timing recovery module, wherein said timing recovery module provides N sampling clocks to said N ADC paths, whereby said N sampling clocks control said N ADC paths to sample a received signal at said receiver input; and means for adjusting each of said N sampling signals to reduce sampling phase errors in said N ADC paths. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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Specification