Implantable sensor and integrity tests therefor

• US 7,778,679 B2
• Filed: 11/30/2001
• Issued: 08/17/2010
• Est. Priority Date: 10/20/1997
• Status: Active Grant

• Current Assignee: Alfred E. Mann Foundation For Scientific Research
• Original Assignee: Alfred E. Mann Foundation For Scientific Research
• Inventors: Schulman, Joseph H., Canfield, Lyle D., Shah, Rajiv, Gord, John C.
• Primary Examiner(s): Marmor, II; Charles A
• Assistant Examiner(s): Natnithithadha; Navin
• Application Number:
  US10/000,977
• Publication Number:
  US 20020042561A1
• Time in Patent Office: 3,182 Days
• Field of Search: 600/300, 600/301, 600345-366, 600/309, 363/671.08, 363/125, 363/127, 363/131, 257/119
• US Class Current: 600/345
• CPC Class Codes: A61B 5/14532 for measuring glucose, e.g. by tissue impedance measurement

Abstract

An implantable sensor includes electronic circuitry for automatically performing on a periodic basis, e.g., every 1 to 24 hours, specified integrity tests which verify proper operation of the sensor.

Claims

1. An implantable sensor including a low power rectifier circuit, the low power rectifier circuit comprising:

a hermetically sealed case;

a pair of external input lines on which a pulsed power signal is received into said case;

a pair of output lines on which an operating voltage is made available;

N-MOS and P-MOS field effect transistor (FET) switches inside said case that automatically connect an appropriate one of the pair of input lines to an appropriate one of the pair of output lines in synchrony with positive and negative pulses of the pulsed power signal; and

a filter capacitor inside said case connected between the pair of output lines,

wherein a data signal on the pair of external input lines supplies power to the circuit.

2. The implantable sensor including the low power rectifier circuit of claim 1, further comprising a pulsed power signal source arranged outside said case, wherein said pulsed power signal source operates by inductive coupling of a high frequency AC signal to generate the pulsed power signal on said input lines.

3. The implantable sensor including the low power rectifier circuit of claim 1 wherein the N-MOS and P-MOS FET switches comprise:

a first P-MOS FET that, when turned on, connects a first one of the input lines to a first one of the output lines;

a second P-MOS FET that, when turned on, connects a second one of the input lines to the first one of the output lines;

a first N-MOS FET that, when turned on, connects the first one of the input lines to a second one of the output lines;

a second N-MOS FET that, when turned on, connects the second one of the input lines to the second one of the output lines; and

a detector circuit that, when there is a positive pulse within the pulsed power signal on the first one of the input lines relative to the second one of the input lines, turns the first P-MOS FET on, the second N-MOS FET on, and maintains the second P-MOS off, and the first N-MOS FET off; and

, when there is a negative pulse within the pulsed power signal on the first one of the input lines relative to the second one of the input lines, turns the second P-MOS FET on, the first N-MOS FET on, and maintains the first P-MOS FET off, and the second N-MOS FET off.

4. The implantable sensor including the low power rectifier circuit of claim 3 wherein the detector circuit comprises:

a first detector circuit that in response to a positive pulse within the pulsed power signal on the first one of the input lines relative to the second one of the input lines exceeding a first threshold value turns on the first P-MOS FET, and that in response to a negative pulse within the pulsed power signal on the first one of the input lines relative to the second one of the input lines exceeding a second threshold value turns on the first N-MOS FET; and

a second detector circuit that in response to a positive pulse within the pulsed power signal on the second one of the input lines relative to the first one of the input lines exceeding the first threshold value turns on the second P-MOS FET, and that in response to a negative pulse within the pulsed power signal on the second one of the input lines relative to the first one of the input lines exceeding the second threshold value turns on the second N-MOS FET.

5. The implantable sensor including the low power rectifier circuit of claim 3 wherein the detector circuit comprises:

a first detector circuit that turns the first P-MOS FET on only when there is a positive pulse within the pulsed power signal on the first one of the input lines relative to the second one of the input lines that has an amplitude exceeding a first threshold value;

a second detector circuit that turns the second P-MOS FET on only when there is a positive pulse within the pulsed power signal on the second one of the input lines relative to the first one of the input lines that has an amplitude exceeding the first threshold value;

a third detector circuit that turns the first N-MOS FET on only when there is a negative pulse within the pulsed power signal on the first one of the input lines relative to the second one of the input lines that has a negative amplitude exceeding a second threshold value; and

a fourth detector circuit that turns the second N-MOS FET on only when there is a negative pulse within the pulsed power signal on the second one of the input lines relative to the first one of the input lines that has a negative amplitude exceeding the second threshold value.

6. The implantable sensor including the low power rectifier circuit of claim 5 wherein all of the first, second, third and fourth switches and respective detector circuits are part of a single integrated circuit.

7. The implantable sensor including the low power rectifier circuit of claim 5 wherein each of the first, second, third and fourth detector circuits include a complementary N-MOS and P-MOS transistor pair connected as a detector circuit to be biased ON only when a pulse of the pulsed power signal present on the pair of input lines has an amplitude greater than a bias reference voltage.

8. The implantable sensor including the low power rectifier circuit of claim 7 wherein the complementary N-MOS and P-MOS transistor pair of each detector circuit has a first bias reference voltage connected to a gate terminal of its P-MOS transistor, and a second bias reference voltage connected to a gate terminal of its N-MOS transistor.

9. The implantable sensor including the low power rectifier circuit of claim 8 further including a bias generator circuit that generates the first and second reference voltages, and wherein the bias generator circuit includes circuitry for dynamically setting the first and second reference voltages to an operational level when a power signal is present on the pair of input lines, and to a low power standby level when a power signal is not present on the pair of input lines.

10. The implantable sensor including the low power rectifier circuit of claim 9 wherein the bias generator circuit generates a first bias signal that is a fixed amount less than the voltage present on the filter capacitor as sensed on the first voltage rail, and wherein the first detector circuit closes the first switch to connect the first input line to the first voltage rail only when the incoming voltage signal on the first input line exceeds the first bias signal.

11. The implantable sensor including the low power rectifier circuit of claim 10 wherein the second detector circuit closes the second switch to connect the second input line to the first voltage rail only when the incoming voltage signal of the first input line relative to the second input line is a positive voltage greater than the first bias signal.

12. The implantable sensor including the low power rectifier circuit of claim 11 wherein the bias generator circuit includes circuitry for dynamically changing the first bias signal from a first value to a second value whenever an incoming voltage signal is present on the first input line relative to the second input line.

13. The implantable sensor including the low power rectifier circuit of claim 9 wherein the bias generator circuit generates a second bias signal that is a fixed amount smaller than a negative voltage present on the filter capacitor as sensed at the second voltage rail relative to the first voltage rail, and wherein the third detector circuit closes the third switch to connect the first input line to the second voltage rail only when the incoming voltage signal on the first input line relative to the second voltage line is a negative voltage greater than the second bias signal.

14. The implantable sensor including the low power rectifier circuit of claim 13 wherein the fourth detector circuit closes the fourth switch to connect the second input line to the second voltage rail only when the incoming voltage signal on the second input line relative to the first input line is a negative voltage greater than the second bias signal.

15. The implantable sensor including the low power rectifier circuit of claim 14 wherein the bias generator circuit includes circuitry for dynamically changing the second bias signal from a first value to a second value whenever an incoming voltage signal is present on the second input line relative to the first input line.

16. The implantable sensor including the low power rectifier circuit of claim 8 further including a complementary N-MOS and P-MOS inverter circuit interposed between each detector circuit and the respective first/second P-MOS/N-MOS FET switch controlled by the detector circuit.

17. The implantable sensor including the low power rectifier circuit of claim 1 further including a startup voltage source for providing a voltage to the filter capacitor connected between the pair of output lines at a time when no operating voltage is present on said filter capacitor.

18. The implantable sensor including the low power rectifier circuit of claim 17 wherein the startup voltage source comprises parasitic diodes within the N-MOS FET switches, and parasitic PNP bipolar transistors within the P-MOS FET switches, which parasitic diodes and transistors are sufficiently forward biased by an initial power signal on the pair of input lines to cause an initial operating voltage derived from the initial power signal to be stored on said filter capacitor.

19. The implantable sensor including the low power rectifier circuit of claim 1 wherein the pulsed power signal comprises a pulse train of biphasic pulses, each biphasic pulse of the pulse train having a negative pulse and a positive pulse.

20. The implantable sensor including the low power rectifier circuit of claim 19 wherein the frequency of the biphasic pulses in the pulse train ranges from 10 to 500,000 biphasic pulses per second, and wherein each positive and negative pulse within each biphasic pulse has a pulse width of between about 1 to 3 microseconds.

21. The implantable sensor including the low power rectifier circuit of claim 1 further including:

a sensor circuit that derives its operating power from the filter capacitor; and

is enclosed in the hermetically sealed case.

22. The implantable sensor including the low power rectifier circuit of claim 1,

wherein the low power rectifier circuit is a low power switched rectifier circuit;

wherein a first one of the pair of output lines comprises a first voltage rail and a second one of the pair of output lines comprises a second voltage rail;

wherein the filter capacitor is a storage capacitor connected between the first and second voltage rails;

wherein the pair of external input lines comprises first and second input lines;

wherein the N-MOS and P-MOS FET switches comprise;

a first switch connecting the first input line to the first voltage rail;

a second switch connecting the second input line to the first voltage rail;

a third switch connecting the first input line to the second voltage rail; and

a fourth switch connecting the second input line to the second voltage rail;

wherein the low power switched rectifier circuit further comprises;

a detector circuit for each of said first, second, third and fourth switches, respectively, powered by voltage on the storage capacitor, that automatically controls its respective switch to close and open as a function of the voltage signal appearing on the first input line relative to the second input line such that, in concert, the first and fourth switches close and the second and third switches open in response to a positive signal on the first input line relative to the second input line, and such that second and third switches close and the first and fourth switches open in response to a negative signal on the first input line relative to the second input line, whereby the first input line is automatically connected to the first voltage rail and the second input line is automatically connected to the second voltage rail whenever a positive signal appears on the first input line relative to the second input line, and whereby the first input line is automatically connected to the second voltage rail and the second input line is automatically connected to the first voltage rail whenever a negative signal appears on the first input line relative to the second input line; and

a startup voltage source for supplying the storage capacitor with an initial voltage sufficient to power each of the detector circuits;

wherein a data signal on the first and second input lines supplies power to the circuit.

23. The implantable sensor including the low power switched rectifier circuit of claim 22, wherein the data signal is biphasic.

24. The implantable sensor including the low power switched rectifier circuit of claim 22 further including:

a sensor circuit that derives its operating power from the storage capacitor;

wherein the hermetically sealed case encloses the low power switched rectifier circuit and the sensor circuit;

whereby the sealed case containing the sensor circuit and low power rectifier circuit may be implanted within living tissue.

25. The implantable sensor including the low power rectifier circuit of claim 1, further comprising a sensor circuit that derives its operating power from the filter capacitor, wherein the sensor circuit comprises a low power current-to-frequency (I/F) converter circuit for use within an implantable device, the low power I/F converter circuit comprising:

an amplifier having two input terminals and an output terminal, the amplifier for differentially amplifying an electrical signal applied between its two input terminals to provide an amplified output signal appearing on its output terminal;

a first capacitor electrically connected between a first input terminal of the amplifier and a low reference voltage;

a voltage controlled oscillator (VCO) circuit having a voltage-control input terminal and a VCO output terminal, the voltage-control input terminal being connected to the output terminal of the amplifier, the VCO including a generator for generating a frequency output signal F_OUT having a frequency that varies as a function of the magnitude of a voltage applied to the voltage-control input; and

a charge-pump circuit coupled to the first capacitor that pumps a discrete charge off of said first capacitor under control of the frequency output signal F_OUT generated by the VCO.

26. The implantable sensor including the low power rectifier circuit of claim 25 wherein the amplifier, VCO and charge pump circuit all operate using one supply voltage having a first terminal V+, and a second terminal V−

and wherein the low reference voltage is the voltage on a second input terminal of the amplifier which is connected to V−

.

27. The implantable sensor including the low power rectifier circuit of claim 26 wherein the I/F converter circuit is made up of semiconductor circuit components that consume less than 600 nanoamps (na) of current.

28. The implantable sensor including the low power rectifier circuit of claim 25, wherein the low power I/F converter circuit further includes logic circuits responsive to the F_OUT signal to control the charge pump circuit to pump the discrete charge off of the first capacitor at least once during each cycle of the F_OUT signal.

29. The implantable sensor including the low power rectifier circuit of claim 28 wherein the discrete charge pumped off of the first capacitor at least once during each cycle of the F_OUT signal comprises a charge no greater than about 10 pico coulombs.

30. The implantable sensor including the low power rectifier circuit of claim 29 wherein the logic circuits generate a first clock signal from the F_OUT signal having a first phase and a second phase, and wherein the charge pump circuit comprises:

a generator for generating a reference voltage V_REF;

a second capacitor;

a first set of switches for charging the second capacitor to the reference voltage V_REF during the first phase of the first clock signal; and

a second set of switches for connecting the second capacitor across the first capacitor with opposing polarity during the second phase of the first clock signal;

whereby the V_REF charge that accumulates on the second capacitor during the first phase of the first clock signal is pulled off of the first capacitor during the second phase of the first clock signal.

31. The implantable sensor including the low power rectifier circuit of claim 30 wherein the logic circuits generate a second clock signal from the F_OUT signal, and wherein the charge pump circuit further includes:

a third capacitor;

a plurality of switches of the second set of switches charges the third capacitor to the reference voltage V_REF when the second clock signal goes low; and

a plurality of switches of the first set of switches connect the third capacitor across the first capacitor with opposing polarity when the second clock signal goes high;

whereby the V_REF charge that accumulates on the third capacitor when the second clock signal goes low is pulled off of the first capacitor when the second clock signal goes high.

32. The implantable sensor including the low power rectifier circuit of claim 1, further comprising a sensor circuit that derives its operating power from the filter capacitor, wherein the sensor circuit comprises an implantable sensor comprising:

a sensor that generates an analog current as a function of a substance or parameter sensed by the sensor;

a current-to-frequency (I/F) converter circuit that converts the analog current generated by the sensor to a frequency signal, F_OUT having a frequency that varies as a function of the analog current, said I/F converter circuit comprising;

an amplifier having a positive input terminal, a negative input terminal, and an output terminal, the amplifier for differentially amplifying an electrical signal applied between its two input terminals to provide an amplified output signal that appears on its output terminal;

a first capacitor connected between a first input terminal of the amplifier and a low reference voltage;

a voltage controlled oscillator (VCO) circuit having a voltage-control input terminal connected to the output terminal of the amplifier, and a VCO output terminal, the VCO including a generator for generating the frequency signal F_OUT as an output signal of the VCO, the signal F_OUT having a frequency that varies as a function of the magnitude of a voltage applied to the voltage-control input;

a charge-pump circuit coupled to the first capacitor that pumps a discrete charge off of the first capacitor under control of the frequency of the signal F_OUT; and

wherein an analog electrical current from the sensor applied to the first capacitor tends to cause a charge to accumulate on the first capacitor as a function of the magnitude of the electrical current, which charge tends to increase the output voltage of the amplifier so as to increase the frequency of the signal F_OUT which increased frequency causes charge to be pumped off of the first capacitor at an increased rate, wherein the amplifier forces the frequency of the F_OUT signal to whatever rate is needed to maintain the charge on the first capacitor at essentially zero, whereby the frequency of the VCO signal varies as a function of the magnitude of the analog electrical current applied to the first capacitor.

33. The implantable sensor including the low power rectifier circuit of claim 32 wherein the amplifier, VCO and charge pump circuit all operate using one supply voltage having a first terminal V+, and a second terminal V−

, and wherein the low reference voltage is the voltage on a second input terminal of the amplifier which is connected to V−

.

34. The implantable sensor including the low power rectifier circuit of claim 33 wherein the implantable sensor further includes a logic circuitry responsive to the frequency signal F_OUT generated by the VCO to control the charge pump circuit to pump the discrete charge off of the first capacitor at least once during each cycle of the F_OUT signal.

35. The implantable sensor including the low power rectifier circuit of claim 34 wherein the discrete charge pumped off of the first capacitor at least once during each cycle of the F_OUT signal comprises a charge no greater than about 10 pico-coulombs.

36. The implantable sensor including the low power rectifier circuit of claim 32 wherein the current-to-frequency converter is within the hermetically sealed part of said implantable sensor which comprises a hermetically sealed part and a non-hermetically sealed part, with electrical feedthroughs providing electrical connections between said hermetically sealed part and said non-hermetically sealed part.

37. The implantable sensor including the low power rectifier circuit as in claim 1, further comprising a sensor circuit that derives its operating power from the filter capacitor, wherein the sensor circuit comprises a low power current-to-frequency converter comprising:

an amplifier having two input terminals and one output terminal, the amplifier for differentially amplifying an electrical signal applied between its two input terminals to provide an amplified output signal appearing on its output terminal;

a first capacitor connected between a first input terminal of the amplifier and a low reference voltage;

a voltage controlled oscillator (VCO) circuit having a voltage-control input terminal and a VCO output terminal, the voltage-control input terminal being connected to the output terminal of the amplifier, the VCO including a generator for generating a VCO signal having a frequency that varies as a function of the magnitude of a voltage applied to the voltage-control input;

a charge-pump circuit coupled to the first capacitor of the amplifier for pumping a discrete charge off of said first capacitor under control of the frequency of said VCO signal; and

wherein an electrical current applied to the first capacitor tends to cause a charge to accumulate on the first capacitor as a function of the magnitude of the electrical current, which charge tends to increase the output voltage of the amplifier so as to increase the frequency of the VCO signal, which increased VCO frequency causes the charge to be pumped off of the first capacitor at an increased rate, wherein the amplifier forces the frequency of the VCO signal to whatever rate is needed to maintain the charge on the first capacitor at essentially zero, whereby the frequency of the VCO signal varies as a function of the magnitude of the electrical current applied to the first capacitor.

38. The implantable sensor including the low power rectifier circuit of claim 37 wherein the amplifier, VCO and charge pump circuit all operate using one supply voltage having a first terminal V+, and a second terminal V−

, and wherein the low reference voltage is the voltage on a second input terminal of the amplifier which is connected to V−

.

39. The implantable sensor including the low power rectifier circuit of claim 37 wherein the current-to-frequency converter consumes less than about 600 nanoamps (na) of current.

40. The implantable sensor including the low power rectifier circuit of claim 37 wherein the low power current-to-frequency converter further includes a latch logic circuit coupled to the VCO for generating a clock signal for controlling the charge pump circuit to pump the discrete charge off of the first capacitor at least once during each cycle of the clock signal.

41. The implantable sensor including the low power rectifier circuit of claim 40 wherein the discrete charge pumped off of the first capacitor at least once during each cycle of the clock signal comprises a charge no greater than about 10 pico-coulombs.

42. The implantable sensor including the low power rectifier circuit of claim 40 wherein the first clock signal has a first phase and a second phase, and wherein the charge pump circuit comprises:

a second capacitor;

a first set of switches for charging the second capacitor to a reference voltage V_REF during the first phase of the first clock signal;

a second set of switches for connecting the second capacitor across the first capacitor with opposing polarity during the second phase of the first clock signal; and

whereby the V_REF charge that accumulates on the second capacitor during the first phase of the first clock signal is pulled off of the first capacitor during the second phase of the first clock signal.

43. The implantable sensor including the low power rectifier circuit of claim 42 wherein the latch logic circuit coupled to the VCO also generates a second clock signal, and wherein the charge pump circuit further includes:

a third capacitor;

a plurality of switches of the second set of switches charges the third capacitor to the reference voltage V_REF when the second clock signal goes low; and

a plurality of switches of the first set of switches connect the third capacitor across the first capacitor with opposing polarity when the second clock signal goes high;

whereby the V_REF charge that accumulates on the third capacitor when the second clock signal goes low is pulled off of the first capacitor when the second clock signal goes high.

44. The implantable sensor including the low power rectifier circuit of claim 37 wherein the low power current-to-frequency converter is within the hermetically sealed part of said medical device which comprises a hermetically sealed part and a non-hermetically sealed part, with electrical feedthroughs providing electrical connections between said hermetically sealed part and said non-hermetically sealed part.

45. The implantable sensor including the low power rectifier circuit of claim 1, further comprising a sensor circuit that derives its operating power from the filter capacitor, wherein the sensor circuit comprises a very low power current-to-frequency (I/F) converter circuit for use within an implant able device, the I/F converter circuit comprising:

an amplifier having two input terminals and an output terminal, the amplifier for differentially amplifying an electrical signal applied between its two input terminals to provide an amplified output signal appearing on its output terminal;

a first capacitor electrically connected between a first input terminal of the amplifier and a low reference voltage;

a voltage controlled oscillator (VCO) circuit having a voltage-control input terminal and a VCO output terminal, the voltage control input terminal being connected to the output terminal of the amplifier, the VCO including a generator for generating a frequency output signal F_OUT, having a frequency that varies as a function of the magnitude of a voltage applied to the voltage control input;

a charge-pump circuit coupled to the first capacitor that pumps a discrete charge off of said first, capacitor under control of the frequency output signal F_OUT generated by the VCO;

logic circuits responsive to the F_OUT signal to control the charge pump circuit to pump the discrete charge off of the first capacitor at least once during each cycle of the F_OUT signals;

said converter circuit wherein the discrete charge pumped off of the first capacitor at lease once during each cycle of the F_OUT signal comprises a charge no greater than about 10 picocoulombs;

said I/F converter circuit wherein the logic circuits generate a first clock signal from the F_OUT signal having a first phase and a second phase and a second clock signal from the F_OUT signal, and wherein the charge pump circuit comprises a generator for generating a reference voltage V_REF;

a second capacitor;

a first set of switches for charging the second capacitor to the reference voltage V_REF during the first phase of the first clock signal;

a second set of switches for connecting the second capacitor across the first capacitor with opposing polarity during the second phase of the first clock signal;

whereby the V_REF charge that accumulates on the second capacitor during the first phase of the first clock signal is pulled off of the first capacitor during the second phase of the first clock signal;

wherein the charge pump circuit further includes;

a third capacitor;

a plurality of switches of the second set of switches charges the third capacitor to the reference voltage V_REF when the second clock signal goes low; and

a plurality of switches of the first set of switches connect the third capacitor across the first capacitor with opposing polarity when the second clock signal goes high;

whereby the V_REF charge that accumulates on the third capacitor when the second clock signal goes low is pulled off of the first capacitor when the second clock signal goes high.

46. The implantable sensor including the low power rectifier circuit of claim 45 wherein the charge pump circuit pumps the discrete charge off of the first capacitor at least twice during each cycle of the F_OUT signal.

47. The implantable sensor including the low power rectifier circuit of claim 45 wherein the charge pump circuit comprises two capacitors that alternately pump the discrete charge off of the first capacitor.

48. The implantable sensor including the low power rectifier circuit of claim 45 wherein the charge pump circuit comprises:

a circuit that generates a clock signal with a first phase and a second phase from the F_OUT signal;

a generator for generating a reference voltage V_REF;

a second capacitor;

a third capacitor;

wherein during the first phase of the clock signal the second capacitor is charged to the reference voltage V_REF and wherein during the second phase of the clock signal the third capacitor is charge to the reference voltage V_REF; and

wherein during the second phase of the clock signal the V_REF charge that accumulated on the second capacitor during the first phase of the clock signal is pulled off of the first capacitor and wherein during the first phase of the clock signal the V_REF charge that accumulated on the third capacitor during the second phase of the clock signal is pulled off of the first capacitor.

49. The implantable sensor including the low power rectifier circuit of claim 45 wherein the charge pump circuit comprises:

a circuit that generates two non-overlapping clock signals CLK_A and CLK_B from the F_OUT signal;

a generator for generating a reference voltage V_REF;

a second capacitor;

a third capacitor;

wherein when CLK_A goes high the second capacitor is charged to the reference voltage V_REF and wherein when CLK_B goes high the third capacitor is charged to the reference voltage V_REF; and

wherein when CLK_B goes high the V_REF charge that accumulated on the second capacitor is pulled off of the first capacitor and wherein when CLK_A goes high the V_REF charge that accumulated on the third capacitor is pulled off of the first capacitor.

50. The implantable sensor including the low power rectifier circuit of claim 1, wherein

the rectifier circuit is for rectifying the received pulsed power signal and for generating the operating voltage therefrom;

and

electronic circuits within said hermetically sealed case and powered by said operating voltage for performing a specified function.

51. The implantable sensor including the low power rectifier circuit of claim 50 wherein the N-MOS and P-MOS FET switches comprise:

a first P-MOS FET that, when turned on, connects a first one of the input lines to a first one of the output lines;

a second P-MOS FET that, when turned on, connects a second one of the input lines to the first one of the output lines;

a first N-MOS FET that, when turned on, connects the first one of the input lines to a second one of the output lines;

a second N-MOS FET that, when turned on, connects the second one of the input lines to the second one of the output lines;

a first detector circuit that turns the first P-MOS FET switch on only when the power signal on the first one of the input lines relative to the second one of the input lines has a positive amplitude exceeding a first threshold value;

a second detector circuit that turns the second P-MOS FET switch on only when the power signal on the second one of the input lines relative to the first one of the input lines has a positive amplitude exceeding the first threshold value;

a third detector circuit that turns the first N-MOS FET switch on only when the power signal on the first one of the input lines relative to the second one of the input lines has a negative amplitude exceeding a second threshold value; and

a fourth detector circuit that turns the second N-MOS FET switch on only when the power signal on the second one of the input lines relative to the first one of the input lines has a negative amplitude exceeding the second threshold value.

52. The implantable sensor including the low power rectifier circuit of claim 51 wherein each of the first, second, third and fourth detector circuits include a complementary N-MOS and P-MOS transistor pair connected as a detector circuit to be biased ON only when a power signal greater than a bias reference voltage is present on the pair of input lines.

53. The implantable sensor including the low power rectifier circuit of claim 52 wherein the complementary N-MOS and P-MOS transistor pair of each detector circuit has a first bias reference voltage connected to a gate terminal of its P-MOS transistor, and a second bias reference voltage connected to a gate terminal of its N-MOS transistor.

54. The implantable sensor including the low power rectifier circuit of claim 53 further including a bias generator circuit that generates the first and second reference voltages, and wherein the bias generator circuit includes circuitry for dynamically setting the first and second reference voltages to an operational level when a power signal is present on the pair of input lines and to a low power standby level when a power signal is not present on the pair of input lines.

55. The implantable sensor including the low power rectifier circuit of claim 52 further including a complementary N-MOS and P-MOS inverter circuit interposed between each detector circuit and the respective first/second P-MOS/N-MOS FET switch controlled by the detector circuit.

56. The implantable sensor including the low power rectifier circuit of claim 50 further including a startup voltage source for providing a voltage to the filter capacitor connected between the pair of output lines at a time when no operating voltage is present on said filter capacitor.

57. The implantable sensor including the low power rectifier circuit of claim 56 wherein the startup voltage source comprises parasitic diodes within the N-MOS FET switches, and parasitic PNP bipolar transistors within the P-MOS FET switches, which parasitic diodes and transistors are sufficiently forward biased by an initial power signal on the pair of input lines to cause an initial operating voltage derived from the initial power signal to be stored on said filter capacitor.

58. The implantable sensor including the low power rectifier circuit of claim 50, wherein said electronic circuits comprise:

a sensor circuit that is adapted to receive and transmit data on said pair of external input lines, the data signal also being said power signal.

59. The implantable sensor including the low power rectifier circuit of claim 58, wherein said sensor circuit includes a hermetically sealed portion and a non-hermetically sealed portion, wherein said non-hermetically sealed portion has at least one electrode associated therewith, said hermetically sealed portion of the sensor circuit comprising means for measuring a specified parameter within body fluids or tissue to which said at least one electrode is exposed, and means for performing at least one integrity test to verify proper operation of said sensor circuit.

60. An implantable sensor including a low power rectifier circuit, the low power rectifier circuit comprising:

a pair of input lines on which a pulsed power signal is received;

a pair of output lines on which an operating voltage is made available;

N-MOS and P-MOS field effect transistor (FET) switches that automatically connect an appropriate one of the pair of input lines to an appropriate one of the pair of output lines in synchrony with positive and negative pulses of the pulsed power signal; and

a filter capacitor connected between the pair of output lines;

wherein a data signal on the pair of input lines supplies power to the circuit.

61. The implantable sensor including the low power rectifier circuit of claim 60, wherein the data signal is biphasic.