Electronic device with card interface

• US 7,779,192 B2
• Filed: 05/15/2007
• Issued: 08/17/2010
• Est. Priority Date: 03/08/2000
• Status: Expired due to Fees

• Current Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Fujimoto, Akihisa, Suga, Masao, Sakamoto, Hiroyuki, Okamoto, Kosei
• Primary Examiner(s): Cleary; Thomas J
• Application Number:
  US11/798,582
• Publication Number:
  US 20070220192A1
• Time in Patent Office: 1,190 Days
• Field of Search: 710/11, 710/14, 710 62- 63, 710/105, 710301-302, 710/305, 710/16, 713/300
• US Class Current: 710/301
• CPC Class Codes: G06F 13/14 Handling requests for interconnection or transfer
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4018 with data-width conversion
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/409 Mechanical coupling back panels H05K7/1438
• CPC Class Codes: G06F 13/42 Bus transfer protocol, e.g. handshake; Synchronisation
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: H05K 7/10 Plug-in assemblages of components , e.g. IC sockets

Abstract

When initializing a card-shaped device inserted in a card interface, operation mode acquiring means incorporated in an electronic device acquires operation mode information, stored in a register file incorporated in the card-shaped device, by a predetermined procedure using a predetermined pin. Operation mode setting means incorporated in the electronic device executes signal assignment on a plurality of data pins peculiar to an operation mode indicated by the acquired operation mode information, thereby switching a data transfer width, and allowing the card-shaped device to operate in the operation mode.

Claims

1. A device comprising:

connector pins including a plurality of data pins, a command pin, and a power signal pin, such that;

only one of the data pins is configured to receive data in a first operation mode, and

the plurality of data pins are configured to receive data in a second operation mode; and

a set of registers connected to the connector pins, the set of registers storing own operation mode information of the device, the own operation mode information including bus width information which indicates one of the first and second operation modes, wherein;

the command pin is configured to receive a first command for reading operation mode information, the operation mode information indicating one of the first and second operation modes;

one of the connector pins is configured to transmit the operation mode information in response to the first command;

the command pin is configured to receive a second command for reading operation voltage information, the operation voltage information concerning an operation voltage of the device;

one of the connector pins is configured to transmit the operation voltage information in response to the second command; and

the command pin is configured to receive a third command for setting an operation mode of the device into one of the first and second operation modes.

2. The device according to claim 1, wherein the command pin is configured to receive power voltage information concerning a power voltage, the power voltage being supplied externally via the power signal pin.

3. The device according to claim 2, wherein the command pin is configured to transmit a response if the device can operate with the power voltage.

4. The device according to claim 2, wherein the power signal pin is configured to receive an initial voltage before receiving the power voltage information.

5. The device according to claim 4, wherein the initial voltage differs from the power voltage.

6. The device according to claim 1, wherein:

the command pin is configured to receive a fourth command for reading an address assigned to the device, and

the command pin is configured to transmit the address in response to the fourth command.

7. The device according to claim 6, wherein:

the command pin is configured to receive a fifth command for selecting the device, the fifth command including an address indicating a storage device to be selected, and

the device is configured to shift the device to a selected state if the address included in the fifth command is identical to the address assigned to the device.

8. The device according to claim 1, wherein:

the command pin is configured to receive a sixth command for reading identification data, unique to the device, from an electronic device, and

the command pin is configured to transmit the identification data in response to the sixth command.

9. The device according to claim 8, wherein the device is configured to shift the device from a Ready State to an Identification State after transmitting the identification data.

10. The device according to claim 1, further comprising a memory core being connected to the set of registers.

11. A device comprising:

connector pins including a plurality of data pins, a command pin, and a power signal pin, such that;

only one of the data pins is configured to receive data in a first operation mode, and

the plurality of data pins are configured to receive data in a second operation mode; and

a set of registers connected to the connector pins, the set of registers storing own operation mode information of the device, the own operation mode information including bus width information which indicates one of the first and second operation modes, wherein;

the command pin is configured to receive a first command for reading operation mode information, the operation mode information indicating one of the first and second operation modes;

one of the connector pins is configured to transmit the operation mode information in response to the first command;

the command pin is configured to receive a second command for reading operation voltage information, the operation voltage information concerning an operation voltage of the device;

one of the connector pins is configured to transmit the operation voltage information in response to the second command;

the command pin is configured to receive a third command for setting an operation mode of the device into one of the first and second operation modes; and

the device is configured to set the operation mode in response to the third command.

12. The device according to claim 11, wherein the command pin is configured to receive power voltage information concerning a power voltage, the power voltage being supplied via the power signal pin.

13. The device according to claim 12, wherein the command pin is further configured to transmit a response if the device can operate with the power voltage.

14. The device according to claim 12, wherein the power signal pin is configured to receive an initial voltage from an electronic device before receiving the power voltage information.

15. The device according to claim 14, wherein the initial voltage differs from the power voltage.

16. The device according to claim 11, wherein:

the command pin is configured to receive a fourth command for reading an address assigned to the device, and

the command pin is configured to transmit the address in response to the fourth command.

17. The device according to claim 16, wherein:

the command pin is configured to receive a fifth command for selecting the device, the fifth command including an address indicating a storage device to be selected, and

the device is configured to shift the device to a selected state if the address included in the fifth command is identical to the address assigned to the device.

18. The device according to claim 11, wherein:

the command pin is configured to receive a sixth command for reading identification data unique to the device; and

the command pin is configured to transmit the identification data in response to the sixth command.

19. The device according to claim 18, wherein the device is configured to shift the device from a Ready State to an Identification State after transmitting the identification data.

20. The device according to claim 11, further comprising a memory core being connected to the set of registers.