Low power mode for portable computer system

• US 7,779,280 B2
• Filed: 09/18/2006
• Issued: 08/17/2010
• Est. Priority Date: 09/16/2005
• Status: Active Grant

• Current Assignee: Intellectual Ventures I LLC (Intellectual Ventures LLC)
• Original Assignee: Hoshiko LLC (Raoul Management LLC)
• Inventors: Shuster, Gary Stephen
• Primary Examiner(s): CONNOLLY, MARK A
• Application Number:
  US11/532,863
• Publication Number:
  US 20070067655A1
• Time in Patent Office: 1,429 Days
• Field of Search: 713/300, 713/320
• US Class Current: 713/320
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3293 by switching to a less power-consuming processor, e.g. sub-CPU
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A computer system is configured to operate in a normal mode and in a reduced power mode. The normal mode utilizes a primary processor, which operates using a primary operating system. When system power is depleted to a defined level, the primary processor is shut down and certain operations are taken over by a low-power, secondary processor that operates using a secondary operating system.

Claims

1. A computer-implemented method of managing power for a computing device, comprising:

under control of a configured computer system having;

a primary processor in communication with a primary memory that stores machine state data, wherein the primary processor is configured to consume power at a first rate, and

a secondary processor in communication with a secondary memory, wherein the secondary processor is configured to consume power at a second rate that is less than the first rate;

distributing power to the primary processor from a power source responsive to the power source level above a selected level;

distributing power to the secondary processor instead of the primary processor responsive to the power source level at or below the selected level; and

transferring at least a first portion of the machine state data from the primary memory to the secondary memory during switching the power distribution from the primary processor to the secondary processor;

wherein at least a second portion of the machine state data that is not transferred to the secondary memory is stored in a non-volatile memory.

2. The computer-implemented method of claim 1, wherein at least a third portion of the machine state data not transferred to the secondary memory is discarded.

3. The computer-implemented method of claim 1, wherein the first portion of the machine state data that is transferred to the secondary memory is stored in a non-volatile memory upon shutdown of the secondary processor.

4. The computer-implemented method of claim 1, wherein the primary and secondary memories are volatile memories.

5. The computer-implemented method of claim 1, wherein the primary memory comprises primary operating system instructions.

6. The computer-implemented method of claim 5, wherein the secondary memory comprises secondary operating system instructions.

7. The computer-implemented method of claim 6, wherein the secondary processor is in communication with a removeable, non-volatile secondary memory device.

8. The computer-implemented method of claim 7, wherein the non-volatile secondary memory device is accessible from the primary operating system.

9. A computer-readable storage medium encoded thereon with instructions that, when executed, cause a computing system to perform operations comprising:

distributing power to a primary processor from a power source responsive to the power source level above a selected level, the primary processor configured to communicate with a primary memory that stores machine state data and configured to consume power at a first rate during operation;

distributing power to a secondary processor instead of the primary processor responsive to the power source depleted below the selected level, the secondary processor being in communication configured to communicate with a secondary memory and configured to consume power at a second rate less than the first rate;

distributing at least a first portion of the machine state data from the primary memory to the secondary memory during switching the power distribution from the primary processor to the secondary processor; and

storing at least a second portion of the machine state data that is not transferred to the secondary memory in a non-volatile memory.

10. The computer-readable storage medium of claim 9, further configured to discard at least a third portion of the machine state data not transferred to the secondary memory.

11. The computer-readable storage medium of claim 9, further configured to store the first portion of the machine state data that is transferred to the secondary memory in a non-volatile memory upon shutdown of the secondary processor.

12. The computer-readable storage medium of claim 9, wherein the primary and secondary memories are volatile memories.

13. The computer-readable storage medium of claim 9, wherein the primary memory comprises primary operating system instructions.

14. The computer-readable storage medium of claim 13, wherein the secondary memory comprises secondary operating system instructions.

15. The computer-readable storage medium of claim 14, wherein the secondary processor is configured to communicate with a removable, non-volatile secondary memory device.

16. The computer-readable storage medium of claim 15, wherein the non-volatile secondary memory device is accessible from the primary operating system.

17. A computer system, comprising:

a primary processor in communication with a primary memory that stores machine state data, wherein the primary processor is configured to consume power at a first rate, and

a secondary processor in communication with a secondary memory, wherein the secondary processor is configured to consume power at a second rate that is less than the first rate;

a switch configured to distribute power to the primary processor from a power source responsive to the power source level above a selected level and to distribute power to the secondary processor instead of the primary processor responsive to the power source level at or below the selected level; and

wherein the primary processor is further configured to transfer at least a first portion of the machine state data from the primary memory to the secondary memory during switching the power distribution from the primary processor to the secondary processor and at least a second portion of the machine state data that is not transferred to the secondary memory is stored in a non-volatile memory.

18. The system of claim 17, wherein at least a third portion of the machine state data not transferred to the secondary memory is discarded.

19. The system of claim 17, wherein the first portion of the machine state data that is transferred to the secondary memory is stored in a non-volatile memory upon shutdown of the secondary processor.

20. The system of claim 17, wherein the primary and secondary memories are volatile memories.

21. The system of claim 17, wherein the primary memory comprises primary operating system instructions.

22. The system of claim 21, wherein the secondary memory comprises secondary operating system instructions.

23. The system of claim 22, wherein the secondary processor is in communication with a removable, non-volatile secondary memory device.

24. The system of claim 23, wherein the non-volatile secondary memory device is accessible from the primary operating system.

25. The system of claim 23, wherein the switch is controlled by the secondary processor.

26. The system of claim 23, wherein the switch is controlled by a low-power sensor and logic chip integrated with the switch.

27. The system of claim 26, wherein the low-power sensor comprises at least one of a voltage sensor and a current sensor.

28. The system of claim 23, further comprising a first display screen operable with the primary processor when the power source level is above the selected level, wherein the first display screen does not operate when the power source level is below the selected level.

29. The system of claim 28, further comprising a second display screen operable with the secondary processor when the power source level is below the selected level.

30. The system of claim 28, wherein the second display screen does not operate when the power source level is below the selected level.