Memory having an ECC system

• US 7,779,334 B2
• Filed: 06/25/2007
• Issued: 08/17/2010
• Est. Priority Date: 06/26/2006
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Rao, Raviprakrash S., Joshi, Vineet, Earle, Adrian
• Primary Examiner(s): Abraham; Esaw T
• Application Number:
  US11/767,689
• Publication Number:
  US 20080016392A1
• Time in Patent Office: 1,149 Days
• Field of Search: 714/763, 365/185.9
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature

Abstract

An error correction code system for a memory having parity columns of a memory array located within the memory array is provided. The parity columns are grouped together or distributed throughout the memory array. An embodiment includes a multiplexor circuit for selectively coupling only parity bits stored in the parity memory array to I/O circuitry, bypassing ECC logic circuitry and allowing the parity columns to be directly accessible, in a direct access mode or for selectively coupling the parity bits to ECC logic circuitry in an ECC mode.

Claims

1. A memory device having an error correction code system comprising:

a memory array having memory cells arranged in first columns for storing data;

a parity array having memory cells arranged in second columns for storing parity data corresponding to the data, the second columns being arranged in at least a first group and a second group, at least one of the first group and the second group being located between two sub-arrays of the memory array, the first group and the second group being separated by at least one sub-array of the memory array; and

error correction code (ECC) logic circuitry for receiving said data from the memory array and said parity data from the parity array in response to a read operation, the ECC logic circuitry detecting and correcting bit errors in the data.

2. The memory device of claim 1, further including column decoders for selecting one or more of the first columns of the memory array for accessing the data, and for selecting one or more of the second columns of the parity array for accessing the parity data.

3. The memory device of claim 2, further including sense amplifiers coupled to the first columns and the second columns for providing the data and the parity data.

4. The memory device of claim 1, wherein each of said second columns of the parity array are distributed in said memory array.

5. The memory device of claim 4, wherein each of said second columns is located at a position for minimizing a wiring distance between each of said second columns and logic elements of the ECC logic circuitry for receiving parity data bits provided by said second columns.

6. The memory device of claim 1, wherein each of said groups of second columns includes at least two adjacent second columns, the at least two adjacent second columns being located at a position for minimizing a wiring distance to logic elements of the ECC logic circuitry for receiving parity data bits provided by the at least two adjacent second columns.

7. The memory device of claim 1, comprising a parity access switch for selectively coupling the second columns of the parity array to input/output circuitry for bypassing said ECC logic circuitry in a direct access mode, and for selectively coupling the second columns to the ECC logic circuitry in an ECC mode.

8. The memory device of claim 7, wherein said parity access switch includes a multiplexor.

9. A memory device having an error correction code system comprising:

a memory array having memory cells arranged in first columns for storing data;

a parity array having memory cells arranged in second columns for storing parity data corresponding to the data;

error correction code (ECC) logic circuitry for receiving said data from the memory array and said parity data from the parity array, the ECC logic circuitry detecting and correcting bit errors in the data; and

a parity access switch for selectively coupling the second columns of the parity array to input/output circuitry for bypassing said ECC logic circuitry in a direct access mode, and for selectively coupling the second columns to the ECC logic circuitry in an ECC mode.

10. The memory device of claim 9, wherein said parity array has at least one second column located between two sub-arrays of the memory array.

11. The memory device of claim 10, wherein each of the two sub-arrays includes a plurality of first columns.