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Memory having an ECC system

  • US 7,779,334 B2
  • Filed: 06/25/2007
  • Issued: 08/17/2010
  • Est. Priority Date: 06/26/2006
  • Status: Active Grant
First Claim
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1. A memory device having an error correction code system comprising:

  • a memory array having memory cells arranged in first columns for storing data;

    a parity array having memory cells arranged in second columns for storing parity data corresponding to the data, the second columns being arranged in at least a first group and a second group, at least one of the first group and the second group being located between two sub-arrays of the memory array, the first group and the second group being separated by at least one sub-array of the memory array; and

    error correction code (ECC) logic circuitry for receiving said data from the memory array and said parity data from the parity array in response to a read operation, the ECC logic circuitry detecting and correcting bit errors in the data.

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