Methods of making and using integrated and testable sensor array
First Claim
1. A method for making a testable sensor assembly, comprising:
- forming a first sensor array on a first substrate having a first side and a second side, wherein the first sensor array is formed on the first side of the first substrate;
coupling a first semiconductor wafer having a first side and a second side to the first sensor array, wherein the first side of the first semiconductor wafer is coupled to the first sensor array;
thinning one of the second side of the first substrate or the second side of the first semiconductor wafer;
coupling a second semiconductor wafer having a first side and a second side to the sensor assembly, wherein the second semiconductor wafer comprises a plurality of cavities disposed on the first side, and wherein the first side having the plurality of cavities is coupled to the thinned waferthinning the second side of one of the second semiconductor wafer or the other of the first substrate to expose the free internal membranes; and
testing the first sensor array to identify operational and non-operational units in the testable sensor assembly before integration of the sensor assembly with interface electronics.
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Abstract
A method for making a testable sensor assembly is provided. The method includes forming a first sensor array on a first substrate having a first side and a second side, wherein the first sensor array is formed on the first side of the first substrate, coupling a first semiconductor wafer having a first side and a second side to the first sensor array, wherein the first side of the first semiconductor wafer is coupled to the first sensor array, thinning one of the second side of the first substrate or the second side of the first semiconductor wafer, and testing the first sensor array to identify operational and non-operational units in the testable sensor assembly before integration of the sensor assembly with interface electronics.
34 Citations
22 Claims
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1. A method for making a testable sensor assembly, comprising:
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forming a first sensor array on a first substrate having a first side and a second side, wherein the first sensor array is formed on the first side of the first substrate; coupling a first semiconductor wafer having a first side and a second side to the first sensor array, wherein the first side of the first semiconductor wafer is coupled to the first sensor array; thinning one of the second side of the first substrate or the second side of the first semiconductor wafer; coupling a second semiconductor wafer having a first side and a second side to the sensor assembly, wherein the second semiconductor wafer comprises a plurality of cavities disposed on the first side, and wherein the first side having the plurality of cavities is coupled to the thinned wafer thinning the second side of one of the second semiconductor wafer or the other of the first substrate to expose the free internal membranes; and testing the first sensor array to identify operational and non-operational units in the testable sensor assembly before integration of the sensor assembly with interface electronics. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A method for making an integrated and testable MEMS array, comprising:
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forming a first plurality of MEMS cavities on a first substrate having a first side and a second side, wherein the first plurality of cavities are formed on the first side of the first substrate; coupling a second substrate having a first side and a second side to the first plurality of MEMS cavities such that the first side of the second substrate is coupled to the first plurality of MEMS cavities; thinning a second side of one of the first or second substrates such that at least a portion of a semiconductor layer of one of the first or second substrates is exposed; coupling a third substrate having a first side and a second side to the exposed semiconductor layer, wherein the third substrate comprises a second plurality of cavities disposed on the first side, and wherein the second plurality of cavities are coupled to the exposed semiconductor layer, such that the exposed semiconductor layer is configured to act as free internal membranes for the MEMS array; thinning the second side of one of the first, second or third substrates to expose an insulation layer; testing the MEMS array to determine good and bad free internal membranes; coupling a plurality of integrated circuit dies to the exposed insulation layer, wherein each of the plurality of integrated dies is coupled to portions of the good free internal membranes; and removing the second side of the remaining first, second, or third substrates.
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22. A method for making an integrated and testable sensor array, comprising:
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forming a first plurality of sensor cavities on a first side of a first substrate, wherein the first substrate comprises the first side and a second side; coupling a second substrate to the first plurality of sensor cavities; thinning a second side of one of the first or second substrates such that at least a portion of a semiconductor layer of one of the first or second substrates is exposed to form a first exposed semiconductor layer; coupling a semiconductor wafer having a first side and a second side to the first exposed semiconductor layer, wherein the semiconductor wafer comprises a second plurality of sensor cavities disposed on the first side of the semiconductor wafer, and wherein the second plurality of sensor cavities is coupled to the first exposed semiconductor layer, and wherein the first exposed semiconductor layer forms an internal membrane for the second plurality of MEMS cavities; thinning the second side of the other of the first or the second substrates to expose an insulation layer to form the integrated and testable sensor array; and testing the internal membranes of the integrated and testable sensor array to determine operational and non-operational MEMS units of the array before coupling the sensor array with interface electronics.
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Specification