Integrated circuit device

• US 7,781,240 B2
• Filed: 10/26/2006
• Issued: 08/24/2010
• Est. Priority Date: 02/06/1998
• Status: Expired due to Fees

• Current Assignee: Invensas Corporation
• Original Assignee: Tessera Technologies Hungary Kft. (Adeia Inc.)
• Inventors: Badehi, Avner
• Primary Examiner(s): Graybill; David E
• Application Number:
  US11/588,439
• Publication Number:
  US 20070042562A1
• Time in Patent Office: 1,398 Days
• Field of Search: None
• US Class Current: 438/25
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/82 to produce devices, e.g. integrated circuits, each consisting of a plurality of components
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/24051 Conformal with the semiconductor or solid-state device
• CPC Class Codes: H01L 2224/24225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14632 Wafer-level processed structures
• CPC Class Codes: H01L 27/14687 Wafer level processing
• CPC Class Codes: H01L 27/15 including semiconductor components having potential barriers, specially adapted for light emission
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01068 : Erbium [Er]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 31/02002 : Arrangements for conducting electric current to or from the device in operations
• CPC Class Codes: H01L 31/0203 : Containers; Encapsulations , e.g. encapsulation of photodiodesfor photovoltaic devices H01L31/048; for organic photosensitive devices H10K30/80
• CPC Class Codes: H01L 31/02164 : for shielding light, e.g. light blocking layers, cold shields for infrared detectors
• CPC Class Codes: H01L 31/02327 : the optical elements being integrated or being directly associated to the device, e.g. back reflectors optical coatings H01L31/0216
• CPC Class Codes: H01L 31/125 : Composite devices with photosensitive elements and electroluminescent elements within one single body
• CPC Class Codes: H01L 31/186 : Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
• CPC Class Codes: H01L 33/0095 : Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
• CPC Class Codes: H01L 33/44 : characterised by the coatings, e.g. passivation layer or anti-reflective coating
• CPC Class Codes: H01L 33/483 : Containers
• CPC Class Codes: H01L 33/486 : adapted for surface mounting
• CPC Class Codes: H01L 33/52 : Encapsulations
• CPC Class Codes: H01L 33/56 : Materials, e.g. epoxy or silicone resin
• CPC Class Codes: H01L 33/62 : Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

An integrally packaged optronic integrated circuit device (310) including an integrated circuit die (322) containing at least one of a radiation emitter and radiation receiver and having top and bottom surfaces formed of electrically insulative and mechanically protective material, at least one of the surfaces (317) being transparent to radiation, and electrically insulative edge surfaces (314) having pads.

Claims

1. A method of producing packaged optronic integrated circuit devices comprising:

(a) providing a transparent protective layer overlying a first surface of a semiconductor wafer including a plurality of dies;

(b) forming notches extending into the wafer from a second surface of the wafer, the notches being disposed at dice lanes between the dies;

(c) providing an insulating layer overlying the second surface of the wafer and having an outer surface facing away from the wafer;

(d) forming contacts electrically connected to the dies, the contacts extending onto the outer surface of the insulating layer; and

then

(e) severing the transparent protective layer to separate the dies from one another.

2. A method as claimed in claim 1 wherein the wafer includes pads, and wherein the step of forming the notches exposes the pads within the notches.

3. A method as claimed in claim 2 wherein the step of forming contacts includes connecting the contacts to the pads in the notches.

4. A method as claimed in claim 3 wherein the step of forming the notches includes first forming channels extending into the wafer from the second surface and then removing material at the channels to form the notches.

5. A method as claimed in claim 4 wherein the step of forming an insulating layer includes depositing a dielectric material in the channels, and wherein the step of removing material at the channels to form the notches is performed after depositing the dielectric material in the channels.

6. A method as claimed in claim 5 wherein the step of providing an insulating layer includes depositing the dielectric material over the second surface of the wafer as well as in the channels.

7. A method as claimed in claim 6 wherein the step of providing an insulating layer includes attaching a packaging layer over the dielectric material so that the packaging layer defines the outer surface of the insulating layer.

8. A method as claimed in claim 4 wherein the step of removing material within the channels includes cutting away material at the channels.

9. A method as claimed in claim 4 wherein the wafer includes a field insulation layer and the step of forming the channels includes etching the wafer from the second surface of the wafer to the field insulation layer.

10. A method as claimed in claim 9 wherein the field oxide layer is disposed between the pads and the second surface of the wafer, and wherein the step of removing material at the channels is performed so that the notches extend through the field insulation layer.

11. A method as claimed in claim 1 wherein the step of forming the notches is performed so that the notches extend entirely through the wafer.

12. A method as claimed in claim 11 wherein the step of forming the notches is performed so that the notches extend into the transparent protective layer.

13. A method as claimed in claim 1 wherein each die includes at least one of a radiation emitter and a radiation receiver.

14. A method as claimed in claim 1 wherein the step of providing a transparent protective layer includes bonding a transparent plate to the first surface of the wafer.

15. A method as claimed in claim 14 wherein the step of bonding a transparent plate to the wafer includes applying an epoxy between the transparent plate and the first surface of the wafer.

16. A method as claimed in claim 1 further comprising associating at least one spectral filter with the transparent protective layer.

17. A method as claimed in claim 1 further comprising forming one or more lenses on the transparent protective layer.

18. A method as claimed in claim 17 wherein said one or more lenses are formed of the same material as that of the transparent protective layer.

19. A method as claimed in claim 17 wherein said one or more lenses are not formed of the same material as that of the transparent protective layer.

20. A method as claimed in claim 17 wherein said one or more lenses are formed on an outer surface of the transparent protective layer facing away from the wafer.

21. A method as claimed in claim 17 wherein said one or more lenses are formed on an inner surface of the transparent protective layer facing toward the wafer.

22. A method as claimed in claim 1 further comprising forming light coupling bumps on the transparent protective layer.

23. A method as claimed in claim 1 further comprising forming a waveguide on the transparent protective layer.

24. A method claimed in claim 1 and further comprising forming an optical grating on the transparent protective layer.

25. A method as claimed in claim 1 further comprising integrating a polarizer with each said die.

26. A method as claimed in claim 1, wherein the transparent protective layer is transparent to a limited wavelength range of light and each die includes an optronic device sensitive to the limited wavelength range of light.

27. A method of producing packaged optronic integrated circuit devices comprising:

(a) providing a transparent protective layer overlying a first surface of a semiconductor wafer including a plurality of dies;

(b) providing an insulating layer overlying a second surface of the wafer and having an outer surface facing away from the wafer;

(c) forming contacts electrically connected to the dies, the contacts extending onto the outer surface of the insulating layer; and

(d) separating the dies from one another, the step of forming the contacts being performed before completion of the step of separating the dies from one another,

wherein the step of separating the dies from one another includes forming notches extending through the wafer between the dies before forming the contacts and severing the transparent protective layer after forming the contacts, and

wherein the step of forming notches includes forming channels extending into the wafer from the second surface before providing the insulating layer and removing material at the channels after providing the insulating layer.