Wafer level chip size package for MEMS devices and method for fabricating the same

• US 7,781,250 B2
• Filed: 06/04/2008
• Issued: 08/24/2010
• Est. Priority Date: 08/31/2007
• Status: Active Grant

• Current Assignee: China Wafer Level CSP Co., Ltd.
• Original Assignee: China Wafer Level CSP Co., Ltd.
• Inventors: Wang, Wei, Wang, Zhiqi, Xu, Qinqin, Yu, Guoqing
• Primary Examiner(s): CHU, CHRIS C
• Application Number:
  US12/132,641
• Publication Number:
  US 20090057868A1
• Time in Patent Office: 811 Days
• Field of Search: 257/E21.499, 257/E23.021, 257/E23.181, 257/E31.11, 257/432, 257/433, 257/435, 257/690, 257/737, 438/66, 438/68, 438/113, 438/118
• US Class Current: 438/68
• CPC Class Codes: B81B 2207/097 Interconnects arranged on the substrate or the lid, and covered by the package seal
• CPC Class Codes: B81C 1/00301 Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
• CPC Class Codes: B81C 2203/0118 Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present invention provides a wafer level chip size package having cavities within which micro-machined parts are free to move, allowing access to electrical contacts, and optimized for device performance. Also a method for fabricating a wafer level chip size package for MEMS devices is disclosed. This packaging method provides a well packed device with the size much closely to the original one, making it possible to package the whole wafer at the same time and therefore, saves the cost and cycle time.

Claims

1. A method for fabricating a wafer level chip size package for MEMS devices comprising:

providing a substrate wafer having formed thereon MEMS dies, with a plurality of compatible pads disposed at the periphery of each of said MEMS dies on the substrate wafer;

providing a cap substrate, spin coating photo sensitive BCB on said cap substrate, then form a plurality of cavity walls by lithography, the position of each cavity wall is corresponding to that of the MEMS die;

aligning and bonding the substrate wafer with the cap substrate;

thinning the substrate wafer by backside grinding, notching to remove most of the substrate wafer material at scribe lines;

plasma etching at the backside of the substrate wafer to remove the rest of the substrate wafer material and expose part of the compatible pads, trenches being formed;

filling the trenches with insulating materials to cover the exposed compatible pads, spin coating this insulating material on the backside of the substrate wafer as a first insulating layer;

notching again to expose flanks of the compatible pads;

depositing a metal layer on the backside of the substrate wafer by sputtering, forming redistribution leads by lithography and plating;

spin coating a photo sensitive second insulating layer to cover the redistribution leads, making openings by lithography for solder bump forming;

forming solder bumps at the openings of the second insulating layer by screen printing, each solder bump corresponding to a compatible pad; and

dicing the substrate wafer along the scribe lines to singulate the MEMS dies therefrom.

2. The method for fabricating a wafer level chip size package for MEMS devices as claimed in claim 1, further comprising following steps prior to the step of aligning and bonding the substrate wafer with the cap substrate:

forming cavities on the cap substrate by wet etching or plasma etching, utilizing the cavity walls as a mask so that the position of each cavity corresponds to that of the MEMS die.

3. The method for fabricating a wafer level chip size package for MEMS devices as claimed in claim 1, further comprising one or both of following steps:

before cavity formation, making one pair of alignment marks at backside of the cap substrate by lithography, so that the alignment of cavity formation and bonding will be according to these marks; and

before the first notch, spin coating photo resist on backside of the substrate wafer and making photo resist openings at the positions corresponding to those of the compatible pads by backside align system or IR align system;

the first notch will be aligned according to these openings and the photo resist will be utilized as a mask for etching which is the following step of the first notch.

4. The method for fabricating a wafer level chip size package for MEMS devices as claimed in claim 3, wherein the type of photo resist for the first notch is positive.

5. The method for fabricating a wafer level chip size package for MEMS devices as claimed in claim 1, wherein the gases for etching are fluorocarbon or sulfur-fluoride.

6. A method for fabricating a wafer level chip size package for MEMS devices, comprising:

providing a substrate wafer having formed thereon MEMS dies, with a plurality of compatible pads disposed at the periphery of each of said MEMS dies on said wafer;

providing a cap substrate;

screen printing glass frit on the cap substrate to form cavity walls;

aligning and bonding the substrate wafer with the cap substrate;

thinning the substrate wafer by backside grinding, notching to remove most of the substrate wafer material at scribe lines;

plasma etching at the backside of the substrate wafer to remove the rest of the substrate wafer material and expose part of the compatible pads, trenches being formed;

filling the trenches with insulating materials to cover the exposed compatible pads, spin coating this insulating material on the backside of the substrate wafer as a first insulating layer;

notching again to expose flanks of the compatible pads;

depositing a metal layer on the backside of the substrate wafer by sputtering, forming redistribution leads by lithography and UBM technique;

spin coating a photo sensitive second insulating layer to cover the redistribution leads, making openings by lithography for solder bump forming;

forming solder bumps at the openings of the second insulating layer by screen printing, each solder bump corresponding to a compatible pad; and

dicing the substrate wafer along the scribe lines to singulate the MEMS dies therefrom.

7. The method for fabricating a wafer level chip size package for MEMS devices as claimed in claim 6, further comprising following steps prior to the step of screen printing glass frit on the cap substrate to form cavity walls:

depositing a passivation layer on frontside of the cap substrate by PECVD, spin coating photo resist on the passivation layer, making pattern by lithography, the area which need not to be etched should be covered by photo resist;

plasma etching at frontside of the cap substrate, after etching, stripping the photo resist, the pattern of the passivation layer being the same as that of the photo resist; and

making cavities on the cap substrate by wet etching or dry etching, utilizing the passivation layer as a mask so that the position of each cavity corresponds to that of the MEMS die.

8. The method for fabricating a wafer level chip size package for MEMS devices as claimed in claim 6, further comprising one or more of following steps:

before cavity formation, making one pair of alignment marks at the backside of the cap substrate by lithography, so that the alignment of cavity formation and bonding will be according to these marks;

with reference to the marks at the backside, making another pair of alignment marks at frontside of the cap substrate by lithography, so that the screen print will be aligned according to these marks;

before the first notch, spin coating photo resist on the backside of the substrate wafer and making photo resist openings at the positions corresponding to those of the compatible pads by backside align system or IR align system; and

the first notch will be aligned according to these openings and the photo resist will be utilized as a mask for etching which is the following step of the first notch.

9. The method for fabricating a wafer level chip size package for MEMS devices as claimed in claim 8, wherein the type of photo resist for the first notch is positive.

10. The method for fabricating a wafer level chip size package for MEMS devices as claimed in claim 6, wherein the gases for etching are fluorocarbon or sulfur-fluoride.