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Wafer level chip size package for MEMS devices and method for fabricating the same

  • US 7,781,250 B2
  • Filed: 06/04/2008
  • Issued: 08/24/2010
  • Est. Priority Date: 08/31/2007
  • Status: Active Grant
First Claim
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1. A method for fabricating a wafer level chip size package for MEMS devices comprising:

  • providing a substrate wafer having formed thereon MEMS dies, with a plurality of compatible pads disposed at the periphery of each of said MEMS dies on the substrate wafer;

    providing a cap substrate, spin coating photo sensitive BCB on said cap substrate, then form a plurality of cavity walls by lithography, the position of each cavity wall is corresponding to that of the MEMS die;

    aligning and bonding the substrate wafer with the cap substrate;

    thinning the substrate wafer by backside grinding, notching to remove most of the substrate wafer material at scribe lines;

    plasma etching at the backside of the substrate wafer to remove the rest of the substrate wafer material and expose part of the compatible pads, trenches being formed;

    filling the trenches with insulating materials to cover the exposed compatible pads, spin coating this insulating material on the backside of the substrate wafer as a first insulating layer;

    notching again to expose flanks of the compatible pads;

    depositing a metal layer on the backside of the substrate wafer by sputtering, forming redistribution leads by lithography and plating;

    spin coating a photo sensitive second insulating layer to cover the redistribution leads, making openings by lithography for solder bump forming;

    forming solder bumps at the openings of the second insulating layer by screen printing, each solder bump corresponding to a compatible pad; and

    dicing the substrate wafer along the scribe lines to singulate the MEMS dies therefrom.

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