Bulk non-planar transistor having strained enhanced mobility and methods of fabrication

• US 7,781,771 B2
• Filed: 02/04/2008
• Issued: 08/24/2010
• Est. Priority Date: 03/31/2004
• Status: Expired due to Fees

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Cea, Stephen M., Lindert, Nick
• Primary Examiner(s): Parker; Kenneth A
• Assistant Examiner(s): NGUYEN, JOSEPH H
• Application Number:
  US12/025,665
• Publication Number:
  US 20080142841A1
• Time in Patent Office: 932 Days
• Field of Search: 257/202, 257/250, 257/66, 257/65, 257/19, 257/77, 257/18
• US Class Current: 257/66
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H01L 29/78687 with a multilayer structure or superlattice structure

Abstract

A method of a bulk tri-gate transistor having stained enhanced mobility and its method of fabrication. The present invention is a nonplanar transistor having a strained enhanced mobility and its method of fabrication. The transistor has a semiconductor body formed on a semiconductor substrate wherein the semiconductor body has a top surface on laterally opposite sidewalls. A semiconductor capping layer is formed on the top surface and on the sidewalls of the semiconductor body. A gate dielectric layer is formed on the semiconductor capping layer on the top surface of a semiconductor body and is formed on the capping layer on the sidewalls of the semiconductor body. A gate electrode having a pair of laterally opposite sidewalls is formed on and around the gate dielectric layer. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

Claims

1. A semiconductor device comprising:

a strained semiconductor body forming a heterojunction with a substrate semiconductor material, wherein said substrate semiconductor material is a first single crystal comprising a first group IV element, said first single crystal having a first lattice constant, and wherein said strained semiconductor body is a second single crystal comprising a second group IV element, said strained semiconductor body having a top surface and laterally opposite sidewalls;

a semiconductor capping layer on the top surface and on the sidewalls of said strained semiconductor body, wherein said semiconductor capping layer is a third single crystal comprising said first group IV element;

a gate dielectric layer on said semiconductor capping layer on said top surface and on said sidewalls of said strained semiconductor body;

a gate electrode having a pair of laterally opposite sidewalls on said gate dielectric layer; and

a pair of source/drain regions in said strained semiconductor body on opposite sides of said gate electrode, wherein the second single crystal at the heterojunction disposed below the gate dielectric layer is tetragonally distorted to have a second and third lattice constant, the second lattice constant along a plane parallel to the heterojunction and matched with the first lattice constant, the third lattice constant along a plane orthogonal to the heterojunction and mismatched with the first lattice constant.

2. The semiconductor device of claim 1, wherein said semiconductor capping layer has a tensile strain.

3. The semiconductor device of claim 2, wherein said semiconductor capping layer has greater tensile stress on the sidewalls of said strained semiconductor body than on the top surface of said strained semiconductor body.

4. The semiconductor device of claim 2, wherein said source/drain regions are n type conductivity.

5. The semiconductor device of claim 1, wherein said semiconductor substrate comprises a silicon substrate, wherein said strained semiconductor body comprises a silicon germanium alloy and wherein said semiconductor capping layer comprises a silicon film.

6. The semiconductor device of claim 1, wherein said semiconductor capping layer has a compressive strain.

7. The semiconductor device of claim 6, wherein said strained semiconductor body has tetragonal distortion and said semiconductor capping layer has a greater compressive strain on the sidewalls than on the top surface of said strained semiconductor body.

8. The semiconductor device of claim 6, wherein said semiconductor substrate comprises a monocrystalline silicon substrate, wherein said strained semiconductor body comprises a silicon-carbon alloy and wherein said semiconductor capping layer comprises a single crystalline epitaxial silicon film.

9. The semiconductor device of claim 1, wherein said semiconductor substrate comprises a silicon substrate, wherein said strained semiconductor body comprises a silicon germanium epitaxial body, and wherein said semiconductor capping layer comprises a single crystalline epitaxial silicon capping layer.

10. The semiconductor device of claim 1, wherein a width of the semiconductor body is greater than a height of the semiconductor body.

11. The semiconductor device of claim 1, wherein the semiconductor device comprises a tri-gate transistor.

12. The semiconductor device of claim 1, wherein the semiconductor body comprises carbon.

13. The semiconductor device of claim 1, wherein the semiconductor capping layer is orthorhombicly strained by the third lattice constant.