Semiconductor device and manufacturing method thereof

• US 7,781,802 B2
• Filed: 04/26/2007
• Issued: 08/24/2010
• Est. Priority Date: 04/28/2006
• Status: Active Grant

• Current Assignee: Nissan Motor Co., Ltd.
• Original Assignee: Nissan Motor Co., Ltd.
• Inventors: Tanaka, Hideaki, Hoshi, Masakatsu, Shimoida, Yoshio, Hayashi, Tetsuya, Yamagami, Shigeharu
• Primary Examiner(s): Bryant; Kiesha R
• Assistant Examiner(s): Tornow; Mark W
• Application Number:
  US11/790,679
• Publication Number:
  US 20070252171A1
• Time in Patent Office: 1,216 Days
• Field of Search: 257/597, 257/128, 257/199, 257/624, 257/E29.143, 257/E21.062, 438/621
• US Class Current: 257/199
• CPC Class Codes: H01L 21/0465 using masks
• CPC Class Codes: H01L 21/0475 Changing the shape of the semiconductor body, e.g. forming recesses, etching of the semiconductor body H01L21/302
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/267 in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence
• CPC Class Codes: H01L 29/6606 the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
• CPC Class Codes: H01L 29/66136 PN junction diodes
• CPC Class Codes: H01L 29/8613 Mesa PN junction diodes

Abstract

As semiconductor regions in contact with a first main surface of a semiconductor base composed by forming an N− silicon carbide epitaxial layer on an N+ silicon carbide substrate connected to a cathode electrode, there are provided both of an N+ polycrystalline silicon layer of a same conduction type as a conduction type of the semiconductor base and a P+ polycrystalline silicon layer of a conduction type different from the conduction type of the semiconductor base. Both of the N+ polycrystalline silicon layer and the P+ polycrystalline silicon layer are hetero-joined to the semiconductor base, and are ohmically connected to the anode electrode. Moreover, the N+ polycrystalline silicon layer of the same conduction type as the conduction type of the semiconductor base is formed so as to contact the first main surface of the semiconductor base, and the P+ polycrystalline silicon layer of the conduction type different from the conduction type of the semiconductor base is formed in trenches dug on the first main surface of the semiconductor base.

Claims

1. A semiconductor device including a semiconductor base of a predetermined conduction type, a hetero semiconductor region being in contact with a first main surface of the semiconductor base and formed of a semiconductor material different in band gap from the semiconductor base, a first electrode connected to the hetero semiconductor region, and a second electrode connected to the semiconductor base,

wherein the hetero semiconductor region is composed of a first hetero semiconductor region of a same conduction type as the conduction type of the semiconductor base and a second hetero semiconductor region of a conduction type different from the conduction type of the semiconductor base, both of the first hetero semiconductor region and the second hetero semiconductor region are ohmically connected to the first electrode and form a heterojunction to the semiconductor base, the first hetero semiconductor region is formed on the first main surface of the semiconductor base, the first hetero semiconductor region forms a first heterojunction interface at the first main surface, and the second hetero semiconductor region is formed in trenches dug on the first main surface of the semiconductor base so as to form a second heterojunction interface to be deeper in the semiconductor base toward the second electrode than the first heterojunction interface.

2. The semiconductor device according to claim 1, wherein the conduction type of the semiconductor base is an N conduction type.

3. The semiconductor device according to claim 1, wherein the first hetero semiconductor region and the second hetero semiconductor region are in contact with each other.

4. The semiconductor device according to claim 1, wherein the second hetero semiconductor region formed in the trenches dug on the first main surface of the semiconductor base is in contact with the semiconductor base not only by a bottom surface of the second hetero semiconductor region but also by at least a part of side surfaces of the second hetero semiconductor region.

5. The semiconductor device according to claim 1, wherein the trenches dug on the first main surface of the semiconductor base are preset at one or a plurality of positions of the first main surface.

6. The semiconductor device according to claim 1, wherein an angle between a bottom surface of each of the trenches and a side surface of each of the trenches in a portion in which the bottom surface of each of the trenches contacts with the side surface of each of the trenches is at least 90 degrees.

7. The semiconductor device according to claim 1, wherein the portion in which the bottom surface of each of the trenches contacts with the side surface of each of the trenches is formed to have a curved surface at a larger curvature radius than at least a width by which electrons tunnel through an energy barrier on a heterojunction interface formed between the second hetero semiconductor region and the semiconductor base.

8. The semiconductor device according to claim 1, wherein the first electrode is formed so as to contact both of the first hetero semiconductor region and the second hetero semiconductor region, and is thereby ohmically connected to the first hetero semiconductor region and the second hetero semiconductor region.

9. The semiconductor device according to claim 1, wherein the first electrode is formed so as to contact the first hetero semiconductor region, and is thereby ohmically connected to the first hetero semiconductor region, and is ohmically connected to the second hetero semiconductor region through contact holes formed in the first hetero semiconductor region.

10. The semiconductor device according to claim 1, wherein both impurity densities of the first hetero semiconductor region and the second hetero semiconductor region are higher than an impurity density of the semiconductor base.

11. The semiconductor device according to claim 1, wherein field limiting regions configured to limit an electric field of the second electrode, are formed in at least a partial region of bottom portions of the trenches dug on the first main surface of the semiconductor base.

12. The semiconductor device according to claim 11, wherein the field limiting regions are formed of any of a semiconductor of a conduction type different from the conduction type of the semiconductor base, a high resistor, and an insulator.

13. The semiconductor device according to claim 1, wherein a material of the semiconductor base is made of any of silicon carbide, gallium nitride, and diamond.

14. The semiconductor device according to claim 1, wherein a material of the first hetero semiconductor region and/or the second hetero semiconductor region is made of any of monocrystalline silicon, polycrystalline silicon, amorphous silicon, monocrystalline silicon germanium, polycrystalline silicon germanium, and amorphous silicon germanium.

15. The semiconductor device according to claim 1, wherein a material of the first hetero semiconductor region and/or the second hetero semiconductor region is made of any of monocrystalline germanium, polycrystalline germanium, amorphous germanium, monocrystalline gallium arsenide, polycrystalline gallium arsenide, and amorphous gallium arsenide.