Semiconductor constructions containing tubular capacitor storage nodes, and retaining structures along portions of the tubular capacitor storage nodes

• US 7,781,818 B2
• Filed: 11/09/2006
• Issued: 08/24/2010
• Est. Priority Date: 08/30/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Graettinger, Thomas M., Manning, H. Montgomery
• Primary Examiner(s): Stark; Jarrett J
• Application Number:
  US11/595,436
• Publication Number:
  US 20070052115A1
• Time in Patent Office: 1,384 Days
• Field of Search: None
• US Class Current: 257/304
• CPC Class Codes: H01L 28/91 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H01L 29/945 Trench capacitors
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/318 the storage electrode having multiple segments
• CPC Class Codes: Y10S 257/906 Dram with capacitor electrodes used for accessing, e.g. bit line is capacitor plate

Abstract

The invention includes semiconductor constructions, and also includes methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive storage node material within openings in an insulative material to form conductive containers. A retaining structure lattice is formed in physical contact with at least some of the containers, and subsequently the insulative material is removed to expose outer surfaces of the containers. The retaining structure can alleviate toppling or other loss of structural integrity of the container structures. The electrically conductive containers correspond to first capacitor electrodes. After the outer sidewalls of the containers are exposed, dielectric material is formed within the containers and along the exposed outer sidewalls. Subsequently, a second capacitor electrode is formed over the dielectric material. The first and second capacitor electrodes, together with the dielectric material, form a plurality of capacitor devices.

Claims

1. A semiconductor construction, comprising:

a semiconductor substrate;

a plurality of capacitor storage nodes supported by the substrate, individual storage nodes being shaped as hollow tubes extending upwardly from the substrate, the tubes having first ends proximate the substrate and second ends in opposing relation to the first ends;

the second ends having upper portions, lower portions below the upper portions, and steps connecting the upper and lower portions to one another;

the tubes having inner surfaces along their interiors and outer surfaces along their exteriors;

the tubes extending in an array comprising rows and columns;

the second ends of individual tubes having lengths defined by the lengths of the steps, and such lengths of the second ends of the individual tubes extending less than one-fourth of total lengths of the individual tubes;

retaining structures against the upper portions of the second ends and not against the lower portions of the second ends;

the retaining structures extending between and connecting alternating pairs along the rows of storage nodes of the array;

a dielectric material along the inner and outer surfaces of the tubes, the dielectric material being in physical contact with the inner and outer surfaces of the upper and lower portions of the second ends;

an electrically conductive material along the inner and outer surfaces of the tubes and over the dielectric material and in direct physical contact with the dielectric material and capacitively connected with the storage nodes, the electrically conductive material being capacitively connected with both the inner and outer surfaces of the upper and lower portions of the second ends;

wherein,

the second ends of the storage nodes have round peripheries;

the upper portions of the second ends comprise about one-half of the round peripheries of the second ends; and

the lower portions of the second end comprise about one-half of the round peripheries of the second ends.

2. The construction of claim 1 wherein the substrate has an uppermost surface, the retaining structures have lowermost surfaces, and the lowermost surfaces of the retaining structures are spaced from the uppermost surface of the substrate by at least about 10,000 Å

.

3. The construction of claim 2 further comprising an electrically insulative material over the substrate and around lower regions of the storage nodes;

and

wherein said electrically insulative material comprises an uppermost surface that is spaced from the lowermost surface of the retaining structure by at least about 5,000 Å

.

4. The construction of claim 3 wherein the electrically insulative material consists essentially of one or both of undoped silicate glass and silicon nitride.

5. The construction of claim 1 wherein the storage nodes comprise titanium nitride.

6. The construction of claim 1 wherein the retaining structures comprise silicon nitride.

7. The construction of claim 1 wherein the electrically conductive material is directly over both of the upper and lower portions of the second ends.

8. The construction of claim 1 wherein the electrically conductive material is directly over the lower portions of the second ends, and is not directly over the upper portions of the second ends.

9. A semiconductor construction, comprising:

a semiconductor substrate having a planar upper surface;

a plurality of capacitor storage nodes supported by the substrate, individual storage nodes being shaped as hollow tubes extending upwardly from the substrate, the tubes having first ends proximate the substrate and second ends in opposing relation to the first ends;

the tubes having straight outer sidewalls along their exteriors, with such straight outer sidewalls being orthogonal to the planar upper surface of the substrate;

the tubes having straight inner sidewalls along their interiors, with such straight inner sidewalls being orthogonal to the planar upper surface of the substrate;

the second ends of individual tubes having upper portions, lower portions below the upper portions, and steps connecting the upper and lower portions to one another;

the second ends of individual tubes having lengths defined by the lengths of the steps, and such lengths of the second ends of the individual tubes extending less than one-fourth of total lengths of the individual tubes;

the tubes extending in an array comprising rows and columns;

retaining structures against the upper portions of the second ends and not against the lower portions of the second ends;

the retaining structures extending between and connecting alternating pairs along the rows of storage nodes of the array;

a dielectric material along the inner and outer sidewalls of the tubes, the dielectric material being in physical contact with the inner and outer surfaces of the upper and lower portions of the second ends;

an electrically conductive material along the inner and outer surfaces of the tubes and over the dielectric material and in direct physical contact with the dielectric material and capacitively connected with the storage nodes, the electrically conductive material being capacitively connected with both the inner and outer surfaces of the upper and lower portions of the second ends;

wherein,

the second ends of the storage nodes have round peripheries;

the upper portions of the second ends comprise about one-half of the round peripheries of the second ends; and

the lower portions of the second end comprise about one-half of the round peripheries of the second ends.