Semiconductor device with a vertical MOSFET including a superlattice and related methods

• US 7,781,827 B2
• Filed: 01/23/2008
• Issued: 08/24/2010
• Est. Priority Date: 01/24/2007
• Status: Active Grant

• Current Assignee: Atomera Incorporated
• Original Assignee: Mears Technologies Incorporated
• Inventors: Rao, Kalipatnam Vivek
• Primary Examiner(s): Nguyen; Dao H
• Application Number:
  US12/018,260
• Publication Number:
  US 20080179664A1
• Time in Patent Office: 944 Days
• Field of Search: 257/107, 257/329, 257/369, 257/E21.41, 257/E29.056, 257/E29.075, 257/E29.262, 438/157, 438/197, 438/268, 438/285, 438/468, 438/481
• US Class Current: 257/329
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/158 Structures without potential periodicity in a direction perpendicular to a major surface of the substrate, i.e. vertical direction, e.g. lateral superlattices, lateral surface superlattices [LSS]
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor device may include at least one vertical Metal Oxide Semiconductor Field Effect Transistor (MOSFET) on a substrate. The vertical MOSFET may include at least one superlattice including a plurality of laterally stacked groups of layers transverse to the substrate. The vertical MOSFET(s) may further include a gate laterally adjacent the superlattice, and regions vertically above and below the superlattice and cooperating with the gate for causing transport of charge carriers through the superlattice in the vertical direction. Each group of layers of the superlattice may include stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. At least some atoms from opposing base semiconductor portions may be chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor monolayer.

Claims

1. A semiconductor device comprising:

a substrate; and

at least one vertical Metal Oxide Semiconductor Field Effect Transistor (MOSFET) on said substrate and comprising

at least one superlattice comprising a plurality of laterally stacked groups of layers transverse to said substrate,

a gate laterally adjacent said at least one superlattice, and

regions vertically above and below said at least one superlattice and cooperating with said gate for causing transport of charge carriers through said at least one superlattice in the vertical direction,

each group of layers of said superlattice comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, wherein at least some atoms from opposing base semiconductor portions are chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor monolayer.

2. The semiconductor device of claim 1 wherein said at least one superlattice comprises a pair of spaced-apart superlattices;

and further comprising a semiconductor fin between said spaced-apart superlattices.

3. The semiconductor device of claim 1 wherein said gate at least partially surrounds said at least one superlattice.

4. The semiconductor device of claim 1 wherein said gate comprises a gate electrode layer and a gate dielectric layer between said gate electrode layer and said at least one superlattice.

5. The semiconductor device of claim 1 wherein said substrate comprises a semiconductor-on-insulator (SOI) substrate.

6. The semiconductor device of claim 1 wherein said regions comprise at least one drain region and at least one source region.

7. The semiconductor device of claim 6 wherein said at least one source region comprises a plurality of laterally spaced-apart source regions.

8. The semiconductor device of claim 1 wherein said base semiconductor comprises silicon.

9. The semiconductor device of claim 1 wherein said at least one non-semiconductor monolayer comprises oxygen.

10. The semiconductor device of claim 1 wherein said at least one non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.

11. The semiconductor device of claim 1 further comprising:

a dielectric layer overlying said at least one vertical MOSFET;

a respective contact for each of said regions on said dielectric layer; and

a respective via extending between each of said contacts and a corresponding region through said dielectric layer.

12. The semiconductor device of claim 1 wherein said at least one vertical MOSFET comprises a plurality thereof defining an inverter.

13. The semiconductor device of claim 1 wherein said at least one vertical MOSFET comprises at least one n-channel vertical MOSFET and at least one p-channel vertical MOSFET.

14. The semiconductor device of claim 1 wherein said at least one vertical MOSFET comprises a plurality thereof;

and further comprising a respective shallow trench isolation (STI) region between adjacent vertical MOSFETs.

15. A semiconductor device comprising:

a substrate; and

at least one vertical Metal Oxide Semiconductor Field Effect Transistor (MOSFET) on said substrate and comprising

a pair of spaced-apart superlattices each comprising a plurality of laterally stacked groups of layers transverse to said substrate, and a semiconductor fin between said superlattices,

a gate at least partially surrounding said at least one superlattice, and

regions vertically above and below said at least one superlattice and cooperating with said gate for causing transport of charge carriers through said at least one superlattice in the vertical direction,

each group of layers of said superlattice comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, wherein at least some atoms from opposing base semiconductor portions are chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor monolayer.

16. The semiconductor device of claim 15 wherein said regions comprise at least one drain region and at least one source region.

17. The semiconductor device of claim 15 wherein said base semiconductor comprises silicon, and wherein said at least one non-semiconductor monolayer comprises oxygen.

18. The semiconductor device of claim 15 further comprising:

a dielectric layer overlying said at least one vertical MOSFET;

a respective contact for each of said regions on said dielectric layer; and

a respective via extending between each of said contacts and a corresponding region through said dielectric layer.

19. The semiconductor device of claim 15 wherein said at least one vertical MOSFET comprises a plurality thereof defining an inverter.

20. A method for making a semiconductor device comprising:

forming at least one vertical Metal Oxide Semiconductor Field Effect Transistor (MOSFET) on a substrate by at least

forming at least one superlattice comprising a plurality of laterally stacked groups of layers transverse to the substrate,

forming a gate laterally adjacent the at least one superlattice, and

forming regions vertically above and below the at least one superlattice and cooperating with the gate for causing transport of charge carriers through the at least one superlattice in the vertical direction,

each group of layers of the superlattice comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, wherein at least some atoms from opposing base semiconductor portions are chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor monolayer.

21. The method of claim 20 wherein forming the at least one superlattice further comprises forming a pair of spaced-apart superlattices with a semiconductor fin therebetween.

22. The method of claim 20 wherein forming the gate further comprises forming the gate to at least partially surround the at least one superlattice.

23. The method of claim 20 wherein forming the regions comprises forming at least one drain region and at least one source region.

24. The method of claim 20 wherein the base semiconductor comprises silicon, and wherein the at least one non-semiconductor monolayer comprises oxygen.

25. The method of claim 20 further comprising:

forming a dielectric layer overlying the at least one vertical MOSFET;

forming a respective contact for each of the regions on the dielectric layer; and

forming a respective via extending between each of the contacts and a corresponding region through the dielectric layer.

26. The method of claim 20 wherein forming the at least one vertical MOSFET comprises forming a plurality thereof defining an inverter.