Recessed channel transistor and method for preparing the same

• US 7,781,830 B2
• Filed: 07/16/2008
• Issued: 08/24/2010
• Est. Priority Date: 07/16/2008
• Status: Active Grant

• Current Assignee: Hasdrubal IP LLC (Tanit Ventures Inc.)
• Original Assignee: ProMOS Technologies, Inc.
• Inventors: Li, Ming Yen, Tsai, Bin Siang, Wu, Hsiao Che, Tsai, Wen Li
• Primary Examiner(s): Ha; Nathan W
• Application Number:
  US12/174,110
• Publication Number:
  US 20100013004A1
• Time in Patent Office: 769 Days
• Field of Search: 257/330, 257/331, 257/33, 257/336, 257/E21.41
• US Class Current: 257/331
• CPC Class Codes: H01L 21/28061 the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction H01L21/28052 takes precedence
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Abstract

A recessed channel transistor comprises a semiconductor substrate having a trench isolation structure, a gate structure having a lower block in the semiconductor substrate and an upper block on the semiconductor substrate, two doped regions positioned at two sides of the upper block and above the lower block, and an insulation spacer positioned at a sidewall of the upper block and having a bottom end sandwiched between the upper block and the doped regions. In particular, the two doped regions serves as the source and drain regions, respectively, and the lower block of the gate structure serves as the recessed gate of the recessed channel transistor.

Claims

1. A recessed channel transistor, comprising:

a semiconductor substrate having a trench isolation structure;

a gate structure having a lower block in the semiconductor substrate and an upper block on the semiconductor substrate;

two doped regions positioned at two sides of the upper block and above the lower block; and

an insulation spacer positioned at a sidewall of the upper block and having a bottom end sandwiched between the upper block and the doped regions.

2. The recessed channel transistor of claim 1, wherein the two doped regions are positioned below an upper surface of the trench isolation structure.

3. The recessed channel transistor of claim 1, wherein the lower block serves as a recessed gate and the upper block serves as a word line.

4. The recessed channel transistor of claim 1, wherein the bottom end of the insulation spacer is tapered.

5. The recessed channel transistor of claim 1, wherein the bottom end of the insulation spacer is positioned below an upper surface of the trench isolation structure.

6. The recessed channel transistor of claim 1, further comprising a liner oxide layer sandwiched between the upper block and the insulation spacer.

7. The recessed channel transistor of claim 1, wherein the doped regions include a metal silicide.

8. The recessed channel transistor of claim 7, further comprising a conductive buffer layer positioned on the metal silicide.

9. The recessed channel transistor of claim 8, further comprising a conductive plug positioned on the conductive buffer layer.

10. The recessed channel transistor of claim 9, wherein the insulation spacer is separated from the conductive plug by the conductive buffer layer.

11. The recessed channel transistor of claim 1, when turned on, a carrier channel directly conducting the two doped regions is positioned alongside the lower block.