System method and apparatus for a multi-phase DC-to-DC converter

• US 7,782,032 B2
• Filed: 09/22/2008
• Issued: 08/24/2010
• Est. Priority Date: 12/03/2007
• Status: Active Grant

• Current Assignee: California Polytechnic Corporation, Cal Poly Corporation
• Original Assignee: California Polytechnic Corporation
• Inventors: Ohn, Kay K., Garinto, Dodi, Waters, Ian O., Taufik,
• Primary Examiner(s): Han; Jessica
• Assistant Examiner(s): Gblende; Jeffrey
• Application Number:
  US12/235,597
• Publication Number:
  US 20090140706A1
• Time in Patent Office: 701 Days
• Field of Search: 323/237, 323/244, 323/271, 323/272, 323/282, 323/284, 363/65, 363/69
• US Class Current: 323/272
• CPC Class Codes: H02M 3/1584 with a plurality of power processing stages connected in parallel

Abstract

A multiphase buck DC to DC converter with an input-output LC tank. The multiphase buck DC to DC converter with an input-output LC tank includes multiple synchronous buck DC to DC converter cells. Each one of the synchronous buck DC to DC converter cells having an input node, an output node and a control node. The synchronous buck DC to DC converter cells are arranged in a parallel configuration including having the input nodes of each one of the synchronous buck DC to DC converter cells connected together at a common input node. The synchronous buck DC to DC converter cells are also arranged in pairs of synchronous buck DC to DC converter cells. The output nodes of each one of the pairs of the synchronous buck DC to DC converter cells are connected to corresponding pair output node. Each one of the pairs of the synchronous buck DC to DC converter cells include a capacitor connected between the common input node and the corresponding pair output node and a corresponding output inductor connected between the corresponding pair output node and a common output node. Methods of reducing a DC input voltage are also disclosed. A multiphase buck DC to DC converter with a bypass capacitor is also disclosed.

Claims

1. A multiphase buck DC to DC converter comprising:

a plurality of synchronous buck DC to DC converter cells, each one of the plurality of synchronous buck DC to DC converter cells having an input node, an output node and a control node, the plurality of synchronous buck DC to DC converter cells being arranged in a parallel configuration including having the input nodes of each one of the plurality of synchronous buck DC to DC converter cells connected together at a common input node, the plurality of synchronous buck DC to DC converter cells being arranged in a plurality of pairs of synchronous buck DC to DC converter cells wherein the output nodes of each one of the plurality of pairs of the synchronous buck DC to DC converter cells are connected to corresponding one of a plurality of pair output nodes, wherein each one of the plurality of pairs of the synchronous buck DC to DC converter cells include;

a capacitor connected between the common input node and the corresponding pair output node; and

a corresponding one of a plurality of output inductors connected between the corresponding pair output node and a common output node.

2. The multiphase buck DC to DC converter of claim 1, wherein each one of the plurality of synchronous buck DC to DC converter cells includes:

an input switch having a first voltage source input node, a input switch control node and an input switch output node;

a converter cell inductor having a first end and a second end, wherein the first end of the converter cell inductor is connected to the input switch output node and the second end of the converter cell inductor is connected to the output nodes of the synchronous buck DC to DC converter cell;

a second switch having a second voltage source input node, a second switch control node and a second switch output node, the second switch output node connected to the input switch output node, the input switch output node and the second switch control node coupled to a corresponding control input of the synchronous buck DC to DC converter cell.

3. The multiphase buck DC to DC converter of claim 1, further comprising a controller having a corresponding one of a plurality of control outputs coupled to a corresponding control input of each of the plurality of synchronous buck DC to DC converter cells.

4. The multiphase buck DC to DC converter of claim 3, wherein the controller includes logic for sequentially activating each one of the plurality synchronous buck DC to DC converter cells.

5. The multiphase buck DC to DC converter of claim 3, wherein the controller includes a feedback signal input from the output of the multiphase buck DC to DC converter.

6. A method of reducing a DC input voltage comprising:

applying the DC input voltage to a common input node of a multiphase buck DC to DC converter including;

a plurality of synchronous buck DC to DC converter cells, each one of the plurality of synchronous buck DC to DC converter cells having an input node, an output node and a control node, the plurality of synchronous buck DC to DC converter cells being arranged in a parallel configuration including having the input nodes of each one of the plurality of synchronous buck DC to DC converter cells connected together at the common input node, the plurality of synchronous buck DC to DC converter cells being arranged in a plurality of pairs of synchronous buck DC to DC converter cells wherein the output nodes of each one of the plurality of pairs of the synchronous buck DC to DC converter cells are connected to corresponding one of a plurality of pair output nodes, wherein each one of the plurality of pairs of the synchronous buck DC to DC converter cells include;

a capacitor connected between the common input node and the corresponding pair output node; and

a corresponding one of a plurality of output inductors connected

between the corresponding pair output node and a common output node

sequentially activating each one of the plurality synchronous buck DC to DC converter cells including deactivating a previous one of the plurality synchronous buck DC to DC converter cells before activating a subsequent one of the plurality synchronous buck DC to DC converter cells;

filtering an output of each one of the plurality synchronous buck DC to DC converter cells in an LC tank formed by the corresponding one of a plurality of output inductors and the capacitor connected between the common input node and the corresponding pair output node;

combining the outputs of each one of the plurality synchronous buck DC to DC converter cells at the common output node.

7. A multiphase buck DC to DC converter with a bypass capacitor comprising:

a plurality of synchronous buck DC to DC converter cells, each one of the plurality of synchronous buck DC to DC converter cells having an input node, a converter cell output node and a control node, the plurality of synchronous buck DC to DC converter cells being arranged in a parallel configuration including having the input nodes of each one of the plurality of synchronous buck DC to DC converter cells connected together at a common input node, the plurality of synchronous buck DC to DC converter cells being arranged in a plurality of pairs of synchronous buck DC to DC converter cells wherein the output nodes of each one of the plurality of pairs of the synchronous buck DC to DC converter cells are connected to corresponding one of a plurality of pair output nodes, wherein each one of the plurality of pairs of the synchronous buck DC to DC converter cells include;

a bypass inductor coupled between the corresponding one of a plurality of pair output nodes and a corresponding one of a plurality of bypass nodes

a bypass capacitor connected between the common input node and the corresponding one of a plurality of bypass nodes; and

an auxiliary inductor coupled between the corresponding one of a plurality of bypass nodes and a common output node.

8. The multiphase buck DC to DC converter of claim 7, wherein each one of the plurality of pairs of synchronous buck DC to DC converter cells further includes an additional inductor coupled between the second switch and a ground potential and an additional capacitor coupled between the second switch and the corresponding one of a plurality of pair output nodes.

9. The multiphase buck DC to DC converter of claim 7, further comprising a controller having a corresponding one of a plurality of control outputs coupled to a corresponding control input of each of the plurality of synchronous buck DC to DC converter cells.

10. The multiphase buck DC to DC converter of claim 9, wherein the controller includes logic for sequentially activating each one of the plurality synchronous buck DC to DC converter cells.

11. A method of reducing a DC input voltage comprising:

applying the DC input voltage to a common input node of a multiphase buck DC to DC converter with a bypass filter including;

a plurality of synchronous buck DC to DC converter cells, each one of the plurality of synchronous buck DC to DC converter cells having an input node, a converter cell output node and a control node, the plurality of synchronous buck DC to DC converter cells being arranged in a parallel configuration including having the input nodes of each one of the plurality of synchronous buck DC to DC converter cells connected together at a common input node, the plurality of synchronous buck DC to DC converter cells being arranged in a plurality of pairs of synchronous buck DC to DC converter cells wherein the output nodes of each one of the plurality of pairs of the synchronous buck DC to DC converter cells are connected to corresponding one of a plurality of pair output nodes, wherein each one of the plurality of pairs of the synchronous buck DC to DC converter cells include;

a bypass inductor coupled between the corresponding one of a plurality of pair output nodes and a corresponding one of a plurality of bypass nodes;

a bypass capacitor connected between the common input node and the corresponding one of a plurality of bypass nodes; and

an auxiliary inductor coupled between the corresponding one of a plurality of bypass nodes and a common output node;

sequentially activating each one of the plurality synchronous buck DC to DC converter cells including deactivating a previous one of the plurality synchronous buck DC to DC converter cells before activating a subsequent one of the plurality synchronous buck DC to DC converter cells;

filtering an output of each one of the plurality synchronous buck DC to DC converter cells in an LC tank formed by the corresponding one of a plurality of output inductors and the capacitor connected between the common input node and the corresponding bypass node;

combining the outputs of each one of the plurality synchronous buck DC to DC converter cells at the common output node.