Integrated circuit and method of detecting a signal edge transition

• US 7,782,093 B2
• Filed: 05/23/2007
• Issued: 08/24/2010
• Est. Priority Date: 05/23/2007
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Dray, Cyrille
• Primary Examiner(s): Donovan; Lincoln
• Assistant Examiner(s): Hernandez; William
• Application Number:
  US11/805,305
• Publication Number:
  US 20080290899A1
• Time in Patent Office: 1,189 Days
• Field of Search: 327/24, 365/233.5
• US Class Current: 327/24
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
• CPC Class Codes: H03K 5/1534 Transition or edge detectors

Abstract

The invention relates to an edge transition detector, and a method of operating an edge transition detector. An integrated circuit includes an edge transition detector for producing an output signal at an output node in response to an input signal. The edge transition detector includes a switch coupled to the output node. The edge transition detector includes a logic device with a first input coupled to the input node and an output coupled to a control terminal of the switch to enable the switch to conduct, thereby effecting a transition of the output signal from a first logic level to a second logic level in response to the input signal. A feedback path is provided from the output node to a second input of the logic device to disable switch conductivity when the output signal completes the logic transition from the first logic level to the second logic level.

Claims

1. An integrated circuit having an edge transition detector for producing an output signal at an output node in response to an input signal coupled to an input node, said edge transition detector comprising:

a switch coupled to said output node;

a logic device with a first input coupled to said input node and an output coupled to a control terminal of said switch to enable said switch to conduct, thereby to effect a transition of said output signal from a first logic level to a second logic level in response to said input signal; and

a feedback path from said output node to a second input of said logic device, wherein said feedback path disables said switch conductivity when said output signal completes said transition from said first logic level to said second logic level, and wherein said feedback path to said second input of said logic device includes an S-R flip-flop.

2. The integrated circuit as claimed in claim 1, wherein said switch is enabled to conduct in response to a rising edge of said input signal.

3. The integrated circuit as claimed in claim 1, wherein said switch comprises a PMOS switch.

4. The integrated circuit as claimed in claim 1, wherein said switch is selectively enabled to conduct by a second input signal.

5. The integrated circuit as claimed in claim 4, wherein said switch is selectively enabled to conduct by a falling edge of said second input signal.

6. The integrated circuit as claimed in claim 1, wherein a third input signal is coupled to a control terminal of a second switch to reset said output signal to said first logic level.

7. The integrated circuit as claimed in claim 6, wherein said output signal is reset to said first logic level in response to a rising edge of said third input signal.

8. The integrated circuit as claimed in claim 1, wherein said S-R flip-flop is reset by a second input signal of said edge transition detector coupled to a reset input of said S-R flip-flop.

24. The integrated circuit as claimed in claim 1, wherein the S-R flip-flop comprises a first NOR gate and a second NOR gate, the first NOR gate having an output coupled to an input of the second NOR gate, and the second NOR gate having an output coupled to an input of the first NOR gate.

9. A method of producing an output signal at an output node of an edge transition detector in response to an input signal received at an input node thereof, the method comprising:

applying said received input signal to a logic device;

applying the output of said logic device to a control terminal of a switch coupled to said output node;

enabling said switch to conduct by said logic device in response to said input signal, thereby causing said output signal to make a transition from a first logic level to a second logic level in response to said input signal; and

disabling said switch to conduct with a feedback path from said output node to a second input of said logic device when said output signal completes said transition from said first logic level to said second logic level, wherein disabling said switch further includes disabling said switch to conduct by a signal in said feedback path coupled to a set input of an S-R flip-flop, the output of said S-R flip-flop coupled to said second input of said logic device.

10. The method as claimed in claim 9, wherein said switch is enabled to conduct in response to a rising edge of said input signal.

11. The method as claimed in claim 9, wherein said switch is enabled to conduct in response to a lowered voltage at said control terminal.

12. The method as claimed in claim 9, further including selectively enabling said switch to conduct by said logic device in response to a second input signal to said edge transition detector.

13. The method as claimed in claim 12, wherein said switch is selectively enabled to conduct by a falling edge of said second input signal.

14. The method as claimed in claim 9, further including resetting said output signal to said first logic level with a second switch controlled by a third input signal.

15. The method as claimed in claim 14, wherein said output signal is reset to said first logic level in response to a rising edge of said third input signal.

16. The method as claimed in claim 9, further including applying a falling edge of a second input signal of said edge transition detector to a reset input of said S-R flip-flop to reset said S-R flip-flop.

17. A digital memory device comprising:

an array of memory cells;

a decoder coupled to said array of memory cells;

a control circuit coupled to said decoder to provide a control signal at a control node of said decoder that enables said decoder, said control circuit comprising;

a switch coupled to said control node of said decoder;

a logic device with a first input coupled to a control signal node and an output coupled to a control terminal of said switch to enable said switch to conduct, thereby to effect a transition of said control signal from a first logic level to a second logic level in response to a signal at said control signal node; and

a feedback path from said control node to a second input of said logic device, wherein said feedback path disables conductivity of said switch when said control signal completes said transition from said first logic level to said second logic level, wherein the feedback path includes a S-R flip flop.

18. A digital memory device as claimed in claim 17, wherein said array of memory cells comprises an array of SRAM memory cells.

19. A digital memory device as claimed in claim 17, further including an inverter in said feedback path.

20. A digital memory device as claimed in claim 17, further including a second logic device in said feedback path coupled to a second control signal node.

21. A digital memory device as claimed in claim 17, further including a second switch with a controlled terminal coupled to said control node, said second switch having a control terminal coupled to a third control signal node, wherein a signal at said third control signal node causes said second switch to conduct to transition said output node from said second logic level to said first logic level.

22. A digital memory device as claimed in claim 17, wherein said switch is enabled to conduct in response to a rising edge of said input signal.

23. A digital memory device as claimed in claim 17, wherein said array of memory cells comprises an embedded device.

25. The digital memory device as claimed in claim 17, wherein the S-R flip-flop comprises a first NOR gate and a second NOR gate, the first NOR gate having an output coupled to an input of the second NOR gate, and the second NOR gate having an output coupled to an input of the first NOR gate.