Adaptive signal-feed-forward circuit and method for reducing amplifier power without signal distortion

• US 7,782,141 B2
• Filed: 12/29/2008
• Issued: 08/24/2010
• Est. Priority Date: 12/29/2008
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Kullberg, Brian K., Khuon, Lunal, Witmer, Steven B.
• Primary Examiner(s): NGUYEN, PATRICIA T
• Application Number:
  US12/317,793
• Publication Number:
  US 20100164630A1
• Time in Patent Office: 603 Days
• Field of Search: 330/297, 330/149, 330/127
• US Class Current: 330/297
• CPC Class Codes: H03F 1/0244 Stepped control
• CPC Class Codes: H03F 1/0261 with control of the polarisation voltage or current, e.g. gliding Class A
• CPC Class Codes: H03F 1/3223 using feed-forward H03F1/3211 takes precedence
• CPC Class Codes: H03F 2200/03 the amplifier being designed for audio applications
• CPC Class Codes: H03F 2203/30015 An input signal dependent control signal controls the bias of an output stage in the SEPP
• CPC Class Codes: H03F 3/3022 CMOS common source output SEPP amplifiers H03F3/3008 takes precedence
• CPC Class Codes: H03F 3/68 Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602

Abstract

Digital amplifying circuitry delays a digital data signal (IN_R) to produce an output signal (Vout_R). The delayed digital data signal is converted to an analog signal (Vin_R) for amplifying by an amplifier (10R). Signal amplitude information (S_R[n]) contained in the incoming digital data signal is detected during the delaying. The signal amplitude information is converted to a first control signal (S_Io_NEG[n]) in response to which an adjustable maximum available supply current of the amplifier is produced of least sufficient magnitude to avoid distortion during the amplifying to produce the output signal. The signal amplitude information also is converted to a second control signal (S_AMPLITUDE[n]) in response to which a supply voltage (V_NEG) of the amplifier is controlled.

Claims

1. Circuitry for reducing power in a digital amplifying system, comprising:

a first digital delay circuit for receiving and delaying a first incoming digital data signal which represents a first analog input signal;

a first digital-to-analog conversion circuit for receiving the delayed first digital data signal from the first digital delay circuit and converting the delayed first data to a first analog signal;

a first amplifier for amplifying the first analog signal to produce a first output voltage applied to a first load;

a digital signal processing system for receiving the first incoming data signal, detecting first signal amplitude information contained in the first incoming digital data, and converting the first signal amplitude information to a first digital control signal to optimize power efficiency of the digital amplifying system; and

power conversion circuitry for converting the first digital control signal to an adjustable maximum available supply current in a first supply conductor of the first amplifier circuitry of at least sufficient magnitude to avoid distortion during the amplifying of the first analog signal to produce the first output voltage, wherein the power conversion circuitry includes a charge pump for producing the adjustable maximum available supply current so as to maintain a first supply voltage on the first supply conductor, switching of the charge pump being controlled by a first clock signal.

2. The circuitry of claim 1 wherein the digital signal processing system performs a first mapping function to map the first digital control signal to a first code for selecting a first predetermined frequency of the first clock signal to optimize power consumption of the charge pump.

3. The circuitry of claim 2 including a first digitally controllable oscillator circuit for producing the first clock signal in response to the first code.

4. The circuitry of claim 3 including a programmable DC-DC converter for producing an adjustable second supply voltage which is applied by means of a second supply voltage conductor to a high-side supply terminal of the first amplifier, low-side supply terminals of the charge pump and the DC-DC converter being coupled to a first reference voltage, switching of the DC-DC converter being controlled by a second clock signal.

5. The circuitry of claim 4 wherein the digital processing system converts the first signal amplitude information to a second digital control signal and performs a second mapping function to map the second digital control signal to a second code for selecting a predetermined value of the second supply voltage, the charge pump generating the first bias voltage in response to the second supply voltage.

6. The circuitry of claim 5 wherein the digital processing system converts the first signal amplitude information to a third digital control signal for optimizing power consumption of the DC-DC converter.

7. The circuitry of claim 6 wherein the digital signal processing system performs a third mapping function to map the third digital control signal to a third code for selecting a second predetermined frequency of the second clock signal to optimize power consumption of the DC-DC converter.

8. The circuitry of claim 7 including a second digitally controllable oscillator circuit for producing the second clock signal in response to the third code.

9. The circuitry of claim 1 wherein the first digital delay circuit delays the first incoming digital signal at least enough to ensure that the first analog signal does not arrive at an input of the first amplifier until any voltage droop or voltage ringing of the first supply voltage due to adjustment of the adjustable maximum available supply current in response to the first digital control signal has settled.

10. The circuitry of claim 1 wherein the first incoming digital data signal is initially stored in and then received from a digital storage medium by the first digital-to-analog conversion circuit.

11. The circuitry of claim 1 wherein the digital signal processing system includes a first finite impulse response (FIR) filter that performs a detecting of the first signal amplitude information by receiving and filtering the first incoming digital data.

12. The circuitry of claim 1 wherein the digital signal processing system multiplies each of a plurality of samples of the first signal amplitude information by a digital representation of a gain of the first amplifier and by a digital representation of a load impedance of the first load for each sample of the first signal amplitude information.

13. The circuitry of claim 7 wherein the first digital delay circuit, the first digital-to-analog conversion circuit, the first amplifier, the first load, and the first finite impulse response filter are included in a first signal channel, the circuitry including a second signal channel including a second digital delay circuit which receives and delays a second incoming digital data signal that represents a second analog input signal, a second digital-to-analog conversion circuit for producing a second analog signal, a second amplifier having a low-side supply terminal connected to the first supply conductor for amplifying the second analog signal to produce a second output voltage applied to a second load, and a second finite impulse response filter, all of which are substantially similar to those in the first signal channel, the digital signal processing system receiving the second incoming data signal, detecting second signal amplitude information contained in the second incoming digital data, and combining the second signal amplitude information with the first signal amplitude information to generate the first digital control signal, and the first supply conductor being connected to the low-side supply terminal of the second amplifier, the power conversion circuitry converting the first digital control signal to the adjustable maximum available supply current in the low-side supply terminals of the first and second amplifiers of at least sufficient magnitude to avoid distortion during the amplifying of the first and second analog signals to produce the first and second output voltages.

14. A method for reducing power dissipated in a digital amplifying system, comprising:

delaying an incoming digital data signal;

converting the delayed digital data signal to an analog signal to be amplified by an amplifier to produce an output signal;

during the delaying, detecting signal amplitude information contained in the incoming digital data;

converting the signal amplitude information to a first digital control signal; and

producing an adjustable maximum available supply current of the amplifier in response to the first digital control signal such that the adjustable maximum available supply current of the amplifier has at least sufficient magnitude to avoid causing signal distortion during amplifying of the analog signal by means of the amplifier to produce the output signal by controlling a first clock signal that controls a switching frequency of a charge pump so as to maintain a predetermined value of a first supply voltage on a first supply conductor of the amplifier during time-varying load currents.

15. The method of claim 14 including setting the predetermined value of the first supply voltage in response to a second supply voltage applied to a high-side supply voltage conductor of the amplifier produced by a programmable DC-DC converter, by converting the signal amplitude information to a second digital control signal, controlling the programmable DC-DC converter in response to the second digital control signal to produce a predetermined value of the second supply voltage, and generating the first supply voltage in response to the second supply voltage by means of the charge pump.

16. The method of claim 15 including converting the signal amplitude information to a third digital control signal and controlling a second clock signal that controls a switching frequency of the programmable DC-DC converter in response to the third digital control signal so as to optimize power dissipation in the programmable DC-DC amplifier.

17. The method of claim 14 including multiplying of each of a plurality of samples of the signal amplitude information by a digital representation of a gain of the amplifier and by a digital representation of a load impedance of the load for each sample of the signal amplitude information to produce each of the first and third digital control signals.

18. An apparatus comprising:

a digital signal processing system that receives a digital input signal and a gain signal;

a delay circuit that receive the digital input signal;

a digital-to-analog conversion circuit that is coupled to the delay circuit;

a power converter having;

a DC-DC converter that is coupled to the digital signal processing system and that generates a first voltage; and

a charge pump that is coupled to the digital signal processing system and the DC-DC converter and that generates a second voltage;

an amplifier having an input terminal, a high-side power terminal, and a low-side power terminal, wherein the input terminal of the amplifier is coupled to the delay circuit, and wherein the high-side power terminal is coupled to the DC-DC converter so as to receive the first voltage, and wherein the low-side power terminal is coupled to the charge pump so as to receive the second voltage.

19. The apparatus of claim 18, wherein the DC-DC converter further comprises:

a buck converter that receives an amplitude adjust signal from the digital signal processing system;

a first oscillator that receives a first control signal from the digital signal processing system to generate a first clock signal and that is coupled to the buck converter so as to provide the first clock signal to the buck converter; and

a second oscillator that receives a second control signal from the digital signal processing system to generate a second clock signal and that is coupled to the charge pump so as to provide the second clock signal to the charge pump.

20. The apparatus of claim 19, wherein the digital-to-analog conversion circuit further comprises:

a sigma-delta digital-to-analog converter (DAC) that receives the digital input signal; and

a low pass filter that is coupled between the sigma-delta DAC and the input terminal of the amplifier.

21. The apparatus of claim 20, wherein the charge pump further comprises:

a switching node;

a first switch that is coupled to the buck converter so as to receive the first voltage and that is coupled to the switching node, wherein the first switch is controlled by the second clock signal;

a second switch that is coupled to switching node, wherein the second switch is controlled by an inverse of the second clock signal;

a first capacitor that is coupled to the switching node;

a third switch that is coupled to the first capacitor, wherein the third switch is controlled by the second clock signal; and

a second capacitor that is coupled between the third switch and the low-side power terminal.