Boosted gate voltage programming for spin-torque MRAM array

• US 7,782,661 B2
• Filed: 11/20/2008
• Issued: 08/24/2010
• Est. Priority Date: 04/24/2007
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: MagiQ Technologies, Incorporated
• Inventors: Yang, Hsu Kai
• Primary Examiner(s): Ho; Hoai V
• Assistant Examiner(s): TRAN, ANTHAN
• Application Number:
  US12/313,487
• Publication Number:
  US 20090073756A1
• Time in Patent Office: 642 Days
• Field of Search: 365/48, 365/158, 365/171
• US Class Current: 365/158
• CPC Class Codes: G11C 11/1653 Address circuits or decoders
• CPC Class Codes: G11C 11/1655 Bit-line or column circuits
• CPC Class Codes: G11C 11/1657 Word-line or row circuits
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/1693 Timing circuits or methods
• CPC Class Codes: G11C 11/1697 Power supply circuits
• CPC Class Codes: Y10T 29/49002 Electrical device making

Abstract

A gate voltage boosting circuit provides a voltage boost to a gate of a select switching MOS transistor of a spin-torque MRAM cell to prevent a programming current reduction through an MTJ device of the spin-torque MRAM cell. A spin-torque MRAM cell array is composed of spin-torque MRAM cells that include a MTJ element and a select switching device. A local word line is associated with one row of the plurality of spin-torque MRAM cells and is connected to a gate terminal of the select switching devices of the row of MRAM cells to control activation and deactivation. One gate voltage boosting circuit is placed between an associated global word line and an associated local word line. The gate voltage boosting circuits boost a voltage of a gate of the selected switching device during writing of a logical “1” to the MTJ element of a selected spin-torque MRAM cell.

Claims

1. A spin-torque MRAM cell array comprising:

a plurality of spin-torque MRAM cells arranged in rows and columns, each spin-torque MRAM cell comprising;

a magnetic tunnel junction element, and

a select switching device having a drain terminal connected to a first terminal of the magnetic tunnel junction element;

a plurality of local word lines, each local word line associated with one row of the plurality of spin-torque MRAM cells and connected to a gate terminal of the select switching device of each spin-torque MRAM cell on each row to control activation and deactivation of the select switching device; and

a plurality of gate voltage boosting circuits, each gate voltage boosting circuit placed between an associated global word line of a plurality of global word lines and an associated local word line of the plurality of local word lines to boost a local word line voltage applied to a gate of the select switching device of the selected spin-torque MRAM cell during writing of a first level to the magnetic tunnel junction element of a selected spin-torque MRAM cell when activated by a local word line control signal wherein a gate capacitance of the select switching devices of unselected spin-torque MRAM cells sharing a local word line function as boost capacitors to provide a boost voltage for the gate boosting circuit.

2. The spin-torque MRAM cell array of claim 1 wherein each of the plurality of gate voltage boosting circuits comprises:

a high voltage switching transistor having a drain terminal connected to the global word line associated with the gate voltage boosting circuit, a source connected to the gate of the gate of the select switching device and a gate connected to receive the local word line control signal to activate and deactivate the high voltage switch transistor for boosting the local word line voltage.

3. The spin-torque MRAM cell array of claim 2 wherein each of the plurality of gate voltage boosting circuits further comprises a clamping device to prevent an over boost condition.

4. The spin-torque MRAM cell array of claim 1 further comprising a plurality of bit lines, each bit line associated with one column of the columns of the plurality of spin-torque MRAM cells and connected to a second terminal of the magnetic tunnel junction element.

5. The spin-torque MRAM cell array of claim 1 further comprising a common source line connected to a source of each of the select switching devices of the plurality of spin-torque MRAM cells provide a source or sink for a write current for programming the spin-torque MRAM cell.

6. The spin-torque MRAM cell array of claim 5 further comprising a common source select circuit connected to the common source line for selecting the source or sink for the write current and for precharging the gate capacitance of the select switching devices of the unselected spin-torque MRAM cell.

7. The spin-torque MRAM cell array of claim 6 wherein the common source line select circuit comprises;

a first transistor having a drain terminal connected to a first voltage source and a source terminal connected to the common source line; and

a second transistor having a drain terminal connected to the common source line and a source terminal connected to a ground reference point;

wherein common source line control signals are connected to gates of the first and second transistors to turn on and turn off the first and second transistors to provide a source or sink for the write current through the selected spin-torque MRAM cell during a program operation.

8. The spin-torque MRAM cell array of claim 1 further comprising a plurality of bit line precharge circuits, each bit line precharge circuit associated with one column of the plurality of spin-torque MRAM cells for precharging the associated bit line dependent upon a datum to be written and for precharging the bit lines of the unselected spin-torque MRAM cells and thus the gate capacitances of the unselected spin-torque MRAM cells.

9. The spin-torque MRAM cell array of claim 8 wherein each of the plurality of bit line precharge circuits comprises:

a third transistor having a drain terminal connected to a first voltage source and a source terminal connected to the associated bit line; and

a fourth transistor having a drain terminal connected to the associated bit line and a source terminal connected to a ground reference point;

wherein bit line control signals are connected to gates of the third and fourth transistors to turn on and turn off the third and fourth transistors to control directionality of the write current flow through a selected spin-torque MRAM cell during a program operation.

10. The spin-torque MRAM cell array of claim 1 wherein a selected spin-torque MRAM cell is written to the first level during a first writing step by:

activating the global word line associated with the selected spin-torque MRAM cell at a first time;

activating the local word line control signal to effectively connect the global word line associated with the selected spin-torque MRAM cell and the local word line associated with the selected spin-torque MRAM cell at the first time;

applying a data input signal as the first level to a bit line associated with the selected spin-torque MRAM cell to generate a current to program the magnetic tunnel junction element of the selected spin-torque MRAM cell to the first level at the first time; and

deactivating the local word line control signal to effectively disconnect the global word line associated with the selected spin-torque MRAM cell and the local word line associated with the selected spin-torque MRAM cell at a second time to float the local word line associated with the selected spin-torque MRAM cell for boosting the associated local word line to a higher voltage level to compensate for a rise of a voltage at a source of the select switching device of the selected spin-torque MRAM cell.

11. A spin-torque magnetic random access memory device comprising

a plurality of spin-torque MRAM cell arrays arranged in a plurality of groups, each spin-torque MRAM array comprising:

a plurality of spin-torque MRAM cells arranged in rows and columns, each spin-torque MRAM cell comprising;

a magnetic tunnel junction element, and

a select switching device having a drain terminal connected to a first terminal of the magnetic tunnel junction element;

a plurality of local word lines, each local word line associated with one row of the plurality of spin-torque MRAM cells and connected to a gate terminal of the select switching device of each spin-torque MRAM cell on each row to control activation and deactivation of the select switching device; and

a plurality of gate voltage boosting circuits, each gate voltage boosting circuit placed between an associated global word line of a plurality of global word lines and an associated local word line of the plurality of local word lines to boost a local word line voltage applied to a gate of the select switching device of the selected spin-torque MRAM cell during writing of a first level to the magnetic tunnel junction element of a selected spin-torque MRAM cell when activated by a local word line control signal wherein a gate capacitance of the select switching devices of unselected spin-torque MRAM cells sharing a local word line function as boost capacitors to provide a boost voltage for the gate boosting circuit.

12. The spin-torque magnetic random access memory device of claim 11 wherein each of the plurality of gate voltage boosting circuits comprises:

a high voltage switching transistor having a drain terminal connected to the global word line associated with the gate voltage boosting circuit, a source connected to the gate of the gate of the select switching device and a gate connected to receive the local word line control signal to activate and deactivate the high voltage switch transistor for boosting the local word line voltage.

13. The spin-torque magnetic random access memory device of claim 12 wherein each of the plurality of gate voltage boosting circuits further comprises a clamping device to prevent an over boost condition.

14. The spin-torque magnetic random access memory device of claim 11 wherein the spin-torque MRAM cell array further comprises a plurality of bit lines, each bit line associated with one column of the columns of the plurality of spin-torque MRAM cells and connected to a second terminal of the magnetic tunnel junction element.

15. The spin-torque magnetic random access memory device of claim 11 further comprising a common source line connected to a source of each of the select switching devices of the plurality of spin-torque MRAM cells provide a source or sink for a write current for programming the spin-torque MRAM cell and for precharging the gate capacitance of the select switching devices of the unselected spin-torque MRAM cell.

16. The spin-torque magnetic random access memory device of claim 15 wherein the spin-torque MRAM cell array further comprises a common source select circuit connected to the common source line for selecting the source or sink for the write current.

17. The spin-torque magnetic random access memory device of claim 16 wherein the common source line select circuit comprises;

a first transistor having a drain terminal connected to a first voltage source and a source terminal connected to the common source line; and

a second transistor having a drain terminal connected to the common source line and a source terminal connected to a ground reference point;

wherein common source line control signals are connected to gates of the first and second transistors to turn on and turn off the first and second transistors to provide a source or sink for the write current through the selected spin-torque MRAM cell during a program operation.

18. The spin-torque magnetic random access memory device of claim 11 wherein the spin-torque MRAM cell array further comprises a plurality of bit line precharge circuits, each bit line precharge circuit associated with one column of the plurality of spin-torque MRAM cells and for precharging the bit lines of the unselected spin-torque MRAM cells and thus the gate capacitances of the unselected spin-torque MRAM cells.

19. The spin-torque magnetic random access memory device of claim 18 wherein each of the plurality of bit line precharge circuits comprises:

a third transistor having a drain terminal connected to a first voltage source and a source terminal connected to the associated bit line; and

a fourth transistor having a drain terminal connected to the associated bit line and a source terminal connected to a ground reference point;

wherein bit line control signals are connected to gates of the third and fourth transistors to turn on and turn off the third and fourth transistors to control directionality of the write current flow through a selected spin-torque MRAM cell during a program operation.

20. The spin-torque magnetic random access memory device of claim 11 wherein a selected spin-torque MRAM cell is written to the first level during a first writing step by:

activating the global word line associated with the selected spin-torque MRAM cell at a first time;

activating the local word line control signal to effectively connect the global word line associated with the selected spin-torque MRAM cell and the local word line associated with the selected spin-torque MRAM cell at the first time;

applying a data input signal as the first level to a bit line associated with the selected spin-torque MRAM cell to generate a current to program the magnetic tunnel junction element of the selected spin-torque MRAM cell to the first level at the first time; and

deactivating the local word line control signal to effectively disconnect the global word line associated with the selected spin-torque MRAM cell and the local word line associated with the selected spin-torque MRAM cell at a second time to float the local word line associated with the selected spin-torque MRAM cell for boosting the associated local word line to a higher voltage level to compensate for a rise of a voltage at a source of the select switching device of the selected spin-torque MRAM cell.

21. A method for writing a selected spin-torque MRAM cell in an array of spin-torque MRAM cells to a first level comprising the steps of:

providing a plurality of spin-torque MRAM cells arranged in rows and columns, each spin-torque MRAM cell comprising;

a magnetic tunnel junction element, and

a select switching device having a drain terminal connected to a first terminal of the magnetic tunnel junction element;

providing a plurality of local word lines, each local word line associated with one row of the plurality of spin-torque MRAM cells and connected to a gate terminal of the select switching device of each spin-torque MRAM cell on each row to control activation and deactivation of the select switching device; and

providing a plurality of gate voltage boosting circuits, each gate voltage boosting circuit placed between an associated global word line of a plurality of global word lines and an associated local word line of the plurality of local word lines to boost a local word line voltage applied to a gate of the select switching device of the selected spin-torque MRAM cell during writing of a first level to the magnetic tunnel junction element of a selected spin-torque MRAM cell when activated by a local word line control signal;

activating the global word line associated with the selected spin-torque MRAM cell at a first time;

activating the local word line control signal to effectively connect the global word line associated with the selected spin-torque MRAM cell and the local word line associated with the selected spin-torque MRAM cell at the first time;

applying a data input signal as the first level to a bit line associated with the selected spin-torque MRAM cell to generate a current to program the magnetic tunnel junction element of the selected spin-torque MRAM cell to the first level at the first time;

precharging the gate capacitance of the select switching devices of the unselected spin-torque MRAM cells; and

deactivating the local word line control signal to effectively disconnect the global word line associated with the selected spin-torque MRAM cell and the local word line associated with the selected spin-torque MRAM cell at a second time to float the local word line associated with the selected spin-torque MRAM cell for boosting the associated local word line to a higher voltage level to compensate for a rise of a voltage at a source of the select switching device of the selected spin-torque MRAM cell.

22. A method for forming a spin-torque MRAM cell array comprising the steps of:

forming a plurality of spin-torque MRAM cells arranged in rows and columns, wherein forming each spin-torque MRAM cell comprises the steps of;

forming a magnetic tunnel junction element, and

forming a select switching device having a drain terminal connected to a first terminal of the magnetic tunnel junction element;

forming a plurality of local word lines, wherein forming each local word line comprises the steps of

associating each local word line with one row of the plurality of spin-torque MRAM cells, and

connecting each word line to a gate terminal of the select switching device of each spin-torque MRAM cell on its associated row to control activation and deactivation of the select switching device; and

forming a plurality of gate voltage boosting circuits, wherein forming each gate voltage boosting circuit comprises the steps of;

placing each gate voltage boosting circuit between an associated global word line of a plurality of global word lines and an associated local word line of the plurality of local word lines to boost a local word line voltage applied to a gate of the selected switching device during writing of a first level to the magnetic tunnel junction element of a selected spin-torque MRAM cell when activated by a local word line control signal, wherein a gate capacitance of the select switching devices of unselected spin-torque MRAM cells sharing a local word line function as boost capacitors to provide a boost voltage for the gate boosting circuit.

23. The method for forming a spin-torque MRAM cell array of claim 22 wherein forming each of the plurality of gate voltage boosting circuits comprises the steps of:

forming a high voltage switching transistor;

connecting a drain terminal of the high voltage switching transistor to the global word line associated with the gate voltage boosting circuit;

connecting a source terminal of the high voltage switching transistor to the gate of the select switching device; and

connecting a gate of the high voltage switching transistor to receive the local word line control signal to activate and deactivate the high voltage switch transistor for boosting the local word line voltage.

24. The method for forming a spin-torque MRAM cell array of claim 23 wherein forming each of the plurality of gate voltage boosting circuits further comprises the steps of:

forming a clamping device to prevent an over boost condition;

connecting a first terminal of the clamping device to the source of the high voltage switching transistor and the associated word ling; and

connecting a second terminal of the clamping device to the ground reference point.

25. The method for forming a spin-torque MRAM cell array of claim 22 further comprising the step of forming a plurality of bit lines, wherein forming each bit line comprises the steps of:

associating each bit line with one column of the columns of the plurality of spin-torque MRAM cells; and

connecting each bit line to a second terminal of the magnetic tunnel junction element.

26. The method for forming a spin-torque MRAM cell array of claim 22 further comprising the steps of:

forming a common source line; and

connecting the common source line to a source of each of the select switching devices of the plurality of spin-torque MRAM cells to provide a source or sink for a write current for programming the spin-torque MRAM cell.

27. The method for forming a spin-torque MRAM cell array of claim 26 further comprising the steps of

forming a common source select circuit;

and

connecting the common source select circuit to the common source line for selecting the source or sink for the write current and for precharging the gate capacitance of the select switching devices of the unselected spin-torque MRAM cell.

28. The method for forming a spin-torque MRAM cell array of claim 27 wherein forming the common source line select circuit comprises steps of:

forming a first transistor having a drain terminal connected to a first voltage source and a source terminal connected to the common source line;

forming a second transistor having a drain terminal connected to the common source line and a source terminal connected to a ground reference point; and

connecting common source line control signals to gates of the first and second transistors to turn on and turn off the first and second transistors to provide a source or sink for the write current through the selected spin-torque MRAM cell during a program operation.

29. The method for forming a spin-torque MRAM cell array of claim 22 further comprising the steps of:

forming a plurality of bit line precharge circuits; and

connecting each bit line precharge circuit with one column of the plurality of spin-torque MRAM cells and for precharging the bit lines of the unselected spin-torque MRAM cells and thus the gate capacitances of the unselected spin-torque MRAM cells.

30. The method for forming a spin-torque MRAM cell array of claim 29 wherein forming each of the plurality of bit line precharge circuits comprises the steps of:

forming a third transistor having a drain terminal connected to a first voltage source and a source terminal connected to an associated bit line;

forming a fourth transistor having a drain terminal connected to the associated bit line and a source terminal connected to a ground reference point; and

connecting the bit line control signals to gates of the third and fourth transistors to turn on and turn off the third and fourth transistors to control directionality of the write current flow through a selected spin-torque MRAM cell during a program operation.