Integrated circuit embedded with non-volatile one-time-programmable and multiple-time programmable memory

• US 7,782,668 B2
• Filed: 11/03/2008
• Issued: 08/24/2010
• Est. Priority Date: 11/01/2007
• Status: Expired due to Fees

• Current Assignee: Invensas Corporation
• Original Assignee: Jonker LLC
• Inventors: Liu, David
• Primary Examiner(s): Tran, Michael T
• Application Number:
  US12/264,029
• Publication Number:
  US 20090114972A1
• Time in Patent Office: 659 Days
• Field of Search: 365/185.03, 365/185.24
• US Class Current: 365/185.03
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 2216/10 Floating gate memory cells with a single polysilicon layer
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/60 the control gate being a doped region, e.g. single-poly memory cell

Abstract

A programmable non-volatile device uses a floating gate that functions as a FET gate that overlaps a portion of a source/drain region. This allows a programming voltage for the device to be imparted to the floating gate through capacitive coupling, thus changing the state of the device. The invention can be used in environments such as data encryption, reference trimming, manufacturing ID, security ID, and many other applications.

Claims

1. A two terminal programmable non-volatile device situated on a substrate comprising:

a floating gate;

wherein said floating gate is comprised of a material that is also used as a gate for a transistor device also situated on the substrate and associated with a logic gate and/or a volatile memory;

a source region coupled to a first terminal; and

a drain region coupled to a second terminal; and

an n-type channel coupling said source region and drain region;

wherein the drain region overlaps a sufficient portion of said gate such that a programming voltage for the device applied to said first terminal of said drain region and second terminal of said source region can be imparted to said floating gate through areal capacitive coupling.

2. The programmable device of claim 1 wherein said programming voltage is greater than 5 volts.

3. The programmable device of claim 1 wherein said floating gate can be erased.

4. The programmable device of claim 3 wherein said device can be re-programmed.

5. The programmable device of claim 3 wherein said floating gate is eraseable by an erase voltage applied to said source region.

6. The programmable device of claim 1 wherein a state of said floating gate can be determined by a read signal applied to said drain.

7. The programmable device of claim 6, wherein said read signal is less than about 1 volt.

8. The programmable device of claim 1 wherein said device is part of a programmable array embedded with separate logic circuits and/or memory circuits in an integrated circuit.

9. The programmable device of claim 8 wherein said device is associated with one of the following:

a data encryption circuit;

a reference trimming circuit;

a manufacturing ID; and

/or a security ID.

10. The programmable device of claim 1, wherein said capacitive coupling takes place in a first trench situated in the substrate.

11. The programmable device of claim 10, wherein a set of second trenches in said substrate are used as embedded DRAM.

12. The programmable device of claim 11, further including a second programmable device coupled in a paired latch arrangement such that a datum and its complement are stored in said paired latch.

13. The programmable device of claim 1, wherein a threshold voltage of said device can be set to multiple discrete levels.

14. The programmable device of claim 1, wherein said floating gate is a multi-level structure.

15. The programmable device of claim 1, wherein said device is part of a thin film transistor.

16. The programmable device of claim 1, wherein said floating gate is oriented in a non-planar configuration.

17. The programmable device of claim 1, wherein said floating gate is distributed and includes impurities acting as charge storage sites.

25. The two terminal programmable device of claim 1, wherein said programming voltage causes the device to change from a conducting state to a non-conducting state.

26. The two terminal programmable device of claim 1, wherein said areal capacitive coupling takes place over a C-shaped area.

27. The two terminal programmable device of claim 1, wherein said areal capacitive coupling can be varied.

28. The two terminal programmable device of claim 1, further including a second two terminal programmable device coupled thereto, which second two terminal programmable device has a different amount of areal capacitive coupling.

18. A two terminal programmable device situated on a substrate comprising:

a floating gate;

said floating gate being comprised of a material that includes impurities acting as charge storage sites and is also used as an insulating layer for other non-programmable devices situated on the substrate;

a source region coupled to a first terminal; and

a drain region coupled to a second terminal; and

an n-type channel coupling said source region and drain region;

wherein the drain region overlaps a sufficient portion of said gate such that a programming voltage applied to said first terminal of said drain region and second terminal of said source region can be imparted to said floating gate through areal capacitive coupling.

29. The two terminal programmable device of claim 18, wherein said programming voltage causes the device to change from a conducting state to a non-conducting state.

30. The two terminal programmable device of claim 18, wherein said areal capacitive coupling takes place over a C-shaped area.

31. The two terminal programmable device of claim 18, wherein said floating gate material includes oxide.

19. A two terminal one-time programmable (OTP) device situated on a substrate comprising:

a floating gate;

wherein said floating gate is comprised of a material that is also shared by an interconnect and/or another gate for a transistor device also situated on the substrate and associated with a logic gate and/or a volatile memory;

a source region coupled to a first terminal; and

a drain region coupled to a second terminal and overlapping an areal portion of said floating gate and capacitively coupled thereto; and

an n-type channel coupling said source region and drain region;

wherein a program voltage can be applied to said first terminal and said second terminal;

wherein a threshold of said floating gate can be permanently altered by channel hot electrons caused by said program voltage to store data in the OTP device.

32. The two terminal programmable device of claim 19, wherein said program voltage causes the device to change from a conducting state to a non-conducting state.

33. The two terminal programmable device of claim 19, wherein said areal portion is a C-shaped area.

34. The two terminal programmable device of claim 19, wherein the OTP device can be set to multiple logic levels.

20. A two terminal one-time programmable (OTP) memory device incorporated on a silicon substrate with one or more other additional logic and/or non-OTP memory devices, characterized in that:

a. said OTP memory device has an n-type channel; and

b. any and all regions and structures of said OTP memory device are derived solely from corresponding regions and structures used as components of the additional logic and/or non-OTP memory devices; and

c. said OTP memory device is programmable through a source terminal and a drain terminal using areal capacitive coupling to a floating gate.

35. The two terminal programmable device of claim 20, wherein said OTP memory device changes from a conducting state to a non-conducting state after programming.

36. The two terminal programmable device of claim 20, wherein said areal capacitive coupling takes place over a C-shaped area.

21. A two terminal programmable memory device with a gate, an n-type impurity source coupled to a first terminal and an n-type impurity drain coupled to a second terminal and on a silicon substrate comprising:

an n-type channel; and

wherein the n-type impurity drain overlaps a sufficient portion of said gate such that a programming voltage applied to said second terminal of said n-type impurity drain and said first terminal can be imparted to said gate through areal capacitive coupling;

said gate being adapted to function as a floating gate so that the device has a programmed state defined by an amount of charge stored on said gate by said programming voltage;

further wherein said charge on said floating gate can be erased so as to permit the device to be re-programmed.

37. The two terminal programmable device of claim 21, wherein said programming voltage causes the device to change from a conducting state to a non-conducting state.

38. The two terminal programmable device of claim 21, wherein said areal capacitive coupling takes place over a C-shaped area.

39. The two terminal programmable device of claim 21, wherein said floating gate can be erased by hot hole injection induced by an erase voltage applied to first terminal.

22. A two terminal one-time programmable (OTP) memory device with a gate, an n-type impurity source coupled to a first terminal and an n-type impurity drain coupled to a second terminal and on a silicon substrate comprising:

an n-type channel; and

wherein the n-type impurity drain overlaps a sufficient portion of said gate such that a voltage applied to said second terminal of n-type impurity drain and said first terminal can be imparted to said gate through areal capacitive coupling;

said gate being adapted so that the OTP device has a programmed state defined by a charge state of said gate.

40. The two terminal programmable device of claim 22, wherein said programming voltage causes the device to change from a conducting state to a non-conducting state.

41. The two terminal programmable device of claim 22, wherein said areal capacitive coupling takes place over a C-shaped area.

23. A programmable non-volatile device situated on a substrate comprising:

a floating gate;

wherein said floating gate is comprised of a material that is also used as a gate for a transistor device also situated on the substrate and associated with a logic gate and/or a volatile memory;

a source region; and

a drain region; and

an n-type channel coupling said source region and drain region;

wherein the drain region overlaps a sufficient portion of said gate such that a programming voltage for the device applied to said drain can be imparted to said floating gate through capacitive coupling occurring in a first trench situated in the substrate; and

a second set of trenches situated in the substrate adapted for use as embedded dynamic random access memory (DRAM).

24. A programmable non-volatile device situated on a substrate comprising:

a floating gate associated with a first programmable device;

wherein said floating gate is comprised of a material that is also used as a gate for a transistor device also situated on the substrate and associated with a logic gate and/or a volatile memory;

a source region; and

a drain region; and

an n-type channel coupling said source region and drain region;

wherein the drain region overlaps a sufficient portion of said gate such that a programming voltage for the device applied to said drain can be imparted to said floating gate through capacitive coupling occurring in a first trench situated in the substrate; and

a second programmable device coupled in a paired latch arrangement with the first programmable device such that a datum and its complement are stored in a paired latch.