NAND memory device column charging
First Claim
Patent Images
1. A flash memory device comprising:
- an array of memory cells having a column format arrangement, wherein each column of cells is coupled to a bit line, the bit lines arranged to form a first page and a second page; and
circuitry to apply a voltage to the columns to reduce a column coupling capacitance and maintain the voltage on the columns of the first page as an inactive page while the second page as an active page is accessed.
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Abstract
Embodiments of NAND Flash memory devices and methods recognize that effective column coupling capacitance can be reduced by maintaining a sourced voltage on adjacent columns of an array. Maintaining the columns in a charged state prior to array operations (read, write, and program) reduces current surges and improves data read timing. Devices and methods charge the array columns at pre-charge and following array access operations.
54 Citations
21 Claims
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1. A flash memory device comprising:
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an array of memory cells having a column format arrangement, wherein each column of cells is coupled to a bit line, the bit lines arranged to form a first page and a second page; and circuitry to apply a voltage to the columns to reduce a column coupling capacitance and maintain the voltage on the columns of the first page as an inactive page while the second page as an active page is accessed. - View Dependent Claims (2, 3, 4, 5)
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6. A method of improving data read timing comprising:
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pre-charging all bit lines of a first page and a second page of a flash memory to a specified positive voltage level, the bit lines formed in a staggered arrangement; and performing a logical operation on an active page while all column bit lines of an inactive page are maintained at the positive voltage level. - View Dependent Claims (7, 8, 9, 10)
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11. A flash device comprising:
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a plurality memory cells arranged in columns along bit lines, the bit lines coupled to form logical pages; and a charging device to provide a positive voltage level to the bit lines prior to initiating a memory access operation to reduce a transient current output from the charging device, wherein the logical pages include an active page and an inactive page, and wherein positive voltage to the bit lines associated with the inactive page is maintained during a memory access to the active page. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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Specification