Logical separation and accessing of descriptor memories

• US 7,782,857 B2
• Filed: 04/03/2007
• Issued: 08/24/2010
• Est. Priority Date: 03/22/2002
• Status: Active Grant

• Current Assignee: Juniper Networks Incorporated
• Original Assignee: Juniper Networks Incorporated
• Inventors: Lim, Raymond Marcelino Manese, Libby, Jeffrey G.
• Primary Examiner(s): JAIN, RAJ K
• Application Number:
  US11/695,723
• Publication Number:
  US 20070183425A1
• Time in Patent Office: 1,239 Days
• Field of Search: None
• US Class Current: 370/392
• CPC Class Codes: H04L 2012/5665 Interaction of ATM with other protocols
• CPC Class Codes: H04L 45/00 Routing or path finding of packets in data switching networks routing or path finding in wireless networks H04W40/00
• CPC Class Codes: H04L 45/60 Router architectures
• CPC Class Codes: H04L 49/3009 Header conversion, routing tables or routing tags
• CPC Class Codes: H04L 49/3072 Packet splitting
• CPC Class Codes: H04L 49/602 Multilayer or multiprotocol switching, e.g. IP switching

Abstract

A packet header processing engine includes a memory having a number of distinct portions for respectively storing different types of descriptor information for a header of a packet. A packet header processing unit includes a number of pointers corresponding to the number of distinct memory portions. The packet header processing unit is configured to retrieve the different types of descriptor information from the number of distinct memory portions and to generate header information from the different types of descriptor information.

Claims

1. A network device comprising:

a plurality of parallel processing engines, each processing engine in the plurality of parallel processing engines including;

a lower layer execution unit to;

receive first header information, where the first header information includes template data, tag descriptor data, and lower layer descriptor data, and

process the received first header information to obtain lower layer header data based on the template data, the tag descriptor data, and the lower layer descriptor data, and

a higher layer execution unit to;

receive second header information, and

process the received second header information to obtain higher layer header data, the higher layer execution unit performing the processing of the received second header information in parallel with the lower layer execution unit performing the processing of the received first header information to form a combined header of the lower layer header data and the higher layer header data.

2. The network device of claim 1 further comprising:

a plurality of mailbox registers to store information, the plurality of mailbox registers allowing the lower layer execution unit and the higher layer execution unit to share data.

3. The network device of claim 2 where at least one mailbox register of the plurality of mailbox registers cannot be written to by the lower layer execution unit, and

at least one other mailbox register of the plurality of mailbox registers cannot be written to by the higher layer execution unit.

4. The network device of claim 2 where at least one mailbox register of the plurality of mailbox registers includes a validity bit that indicates whether the one mailbox register is ready to be written or read.

5. The network device of claim 1 further comprising:

a build component to;

receive the lower layer header data from the lower layer execution unit and the higher layer header data from the higher layer execution unit, and

combine the lower layer header data and the higher layer header data to form a header.

6. The network device of claim 1 where one processing engine of the plurality of parallel processing engines loads information relating to a first header simultaneously with unloading information relating to a second header.

7. The network device of claim 1 where the higher layer execution unit includes a plurality of execution sections, one execution section of the plurality of execution sections processing at least a portion of the received second header information, and a second execution section of the plurality of execution sections computes a checksum.

8. The network device of claim 1 further comprising:

a checksum processing element associated with the higher layer execution unit to compute a checksum for the received second header information.

9. The network device of claim 1 further comprising:

a dispatch component to direct information relating to a header to each processing engine in the plurality of parallel processing engines.

10. A method implemented in a network device comprising a plurality of parallel processing engines, the method comprising:

receiving, at a lower layer execution unit in one of the plurality of parallel processing engines, first header information, where the first header information includes template data, tag descriptor data, and lower layer descriptor data;

generating, at the lower layer execution unit, lower layer header data using the template data, the tag descriptor data, and the lower layer descriptor data;

receiving, at a higher layer execution unit in the one of the plurality of parallel processing engines, second header information;

generating, at the higher layer execution unit, higher layer header data using the received second header data, the generating the higher layer header data occurring in parallel with generating the lower layer header data; and

combining the lower layer header data and the higher layer header data to form a combined header.

11. The method of claim 10 further comprising:

transferring first data from the lower layer execution unit to the higher layer execution unit using a first mailbox register; and

transferring second data from the higher layer execution unit to the lower layer execution unit using a second, different mailbox register.