Configurable ports for a host ethernet adapter
First Claim
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1. An Ethernet adapter comprising:
- a plurality of layers for receiving and transmitting packets from and to a processor;
wherein the plurality of layers include a common high speed serializer/deserializer (high speed serdes) for receiving data from and providing data to different speed data sources on the same pins, wherein the high speed serdes is configured in one of several different modes of operation, wherein each of the different modes of operation uses the same reference clock speed and a different phase locked loop multiplication ratio to operate the high speed serdes at a different internal clock rate, and wherein one or more of the different modes further uses data repetition at a bit level to provide a data rate that is different than the internal clock rate for that mode.
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Abstract
A system and method in accordance with the present invention allows for an adapter to be utilized in a server environment that can accommodate both a 10 G and a 1 G source utilizing the same pins. This is accomplished through the use of a high speed serializer/deserializer (high speed serdes) which can accommodate both data sources. The high speed serdes allows for the use of a relatively low reference clock speed on the NIC to provide the proper clocking of the data sources and also allows for different modes to be set to accommodate the different data sources. Finally the system allows for the adapter to use the same pins for multiple data sources.
85 Citations
25 Claims
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1. An Ethernet adapter comprising:
a plurality of layers for receiving and transmitting packets from and to a processor;
wherein the plurality of layers include a common high speed serializer/deserializer (high speed serdes) for receiving data from and providing data to different speed data sources on the same pins, wherein the high speed serdes is configured in one of several different modes of operation, wherein each of the different modes of operation uses the same reference clock speed and a different phase locked loop multiplication ratio to operate the high speed serdes at a different internal clock rate, and wherein one or more of the different modes further uses data repetition at a bit level to provide a data rate that is different than the internal clock rate for that mode.- View Dependent Claims (2, 3, 4, 5, 6, 7, 25)
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8. A network interface controller (NIC) comprising:
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an interface to a private bus of a processor; and an Ethernet adapter coupled to the interface;
the Ethernet adapter comprising a plurality of layers for receiving and transmitting packets from and to the processor;
wherein the plurality of layers include a high speed serializer/deserializer (high speed serdes) for receiving data from and providing data to different speed data sources on the same pins, wherein the high speed serdes is configured in one of several different modes of operation, wherein each of the different modes of operation uses the same reference clock speed and a different phase locked loop multiplication ratio to operate the high speed serdes at a different internal clock rate, and wherein one or more of the different modes further uses data repetition at a bit level to provide a data rate that is different than the internal clock rate for that mode. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A server comprising:
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a processor;
the processor including a private bus; anda network interface controller (NIC) coupled to the private bus, the NIC including an Ethernet adapter;
the Ethernet adapter comprising a plurality of layers for allowing the adapter to receive and transmit packets from and to the processor;
wherein the plurality of layers include a high speed serializer/deserializer (high speed serdes) to receive data from and provide data to different speed data sources on the same pins, wherein the high speed serdes is configured in one of several different modes of operation, wherein each of the different modes of operation uses the same reference clock speed and a different phase locked loop multiplication ratio to operate the high speed serdes at a different internal clock rate, and wherein one or more of the different modes further uses data repetition at a bit level to provide a data rate that is different than the internal clock rate for that mode.
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16. A method for an Ethernet adapter, the Ethernet adapter including a plurality of layers;
- the method comprising;
utilizing the plurality of layers to receive and transmit packets from and to a processor; receiving data from and providing data to different speed data sources on the same pins of the Ethernet adapter; and allowing the configuration of the plurality of layers to different modes of operation;
wherein each of the different modes of operation uses the same reference clock speed and a different phase locked loop multiplication ratio to operate the high speed serdes at a different internal clock rate, and wherein one or more of the different modes further uses data repetition at a bit level to provide a data rate that is different than the internal clock rate for that mode. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24)
- the method comprising;
Specification