Network switch memory interface configuration

• US 7,782,891 B2
• Filed: 10/29/2007
• Issued: 08/24/2010
• Est. Priority Date: 03/17/1999
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Ambe, Shekhar, Kadambi, Shiri
• Primary Examiner(s): JAIN, RAJ K
• Application Number:
  US11/976,862
• Publication Number:
  US 20080056278A1
• Time in Patent Office: 1,030 Days
• Field of Search: None
• US Class Current: 370/438
• CPC Class Codes: H04L 12/18 for broadcast or conference , e.g. multicast
• CPC Class Codes: H04L 12/42 Loop networks
• CPC Class Codes: H04L 12/46 Interconnection of networks
• CPC Class Codes: H04L 12/4625 Single bridge functionality, e.g. connection of two networks over a single bridge
• CPC Class Codes: H04L 12/4641 Virtual LANs, VLANs, e.g. virtual private networks [VPN] LAN interconnection over a bridge based backbone H04L12/462; encapsulation techniques H04L12/4633; routing of packets H04L45/00; packet switches H04L49/00; virtual private networks for security H04L63/0272
• CPC Class Codes: H04L 12/4645 Details on frame tagging routing of packets H04L45/00; support for virtual LAN H04L49/354
• CPC Class Codes: H04L 12/467 Arrangements for supporting untagged frames, e.g. port-based VLANs
• CPC Class Codes: H04L 12/56 Packet switching systems
• CPC Class Codes: H04L 12/5602 Bandwidth control in ATM Networks, e.g. leaky bucket
• CPC Class Codes: H04L 45/24 Multipath
• CPC Class Codes: H04L 45/245 Link aggregation, e.g. trunking
• CPC Class Codes: H04L 45/54 Organization of routing tables
• CPC Class Codes: H04L 45/742 Route cache; Operation thereof
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 47/125 by balancing the load, e.g. traffic engineering
• CPC Class Codes: H04L 47/15 in relation to multipoint traffic arrangements for broadcast or multicast in data networks H04L12/18
• CPC Class Codes: H04L 47/2408 for supporting different services, e.g. a differentiated services [DiffServ] type of service
• CPC Class Codes: H04L 47/2441 relying on flow classification, e.g. using integrated services [IntServ]
• CPC Class Codes: H04L 47/2458 Modification of priorities while in transit
• CPC Class Codes: H04L 47/286 Time to live
• CPC Class Codes: H04L 47/43 : Assembling or disassembling of packets, e.g. segmentation and reassembly [SAR]
• CPC Class Codes: H04L 47/50 : Queue scheduling
• CPC Class Codes: H04L 47/6215 : Individual queue per QOS, rate or priority
• CPC Class Codes: H04L 47/6225 : Fixed service order, e.g. Round Robin
• CPC Class Codes: H04L 47/623 : Weighted service order
• CPC Class Codes: H04L 49/102 : using shared medium, e.g. bus or ring
• CPC Class Codes: H04L 49/109 : Integrated on microchip, e.g. switch-on-chip
• CPC Class Codes: H04L 49/201 : Multicast operation; Broadcast operation
• CPC Class Codes: H04L 49/208 : Port mirroring
• CPC Class Codes: H04L 49/254 : Centralised controller, i.e. arbitration or scheduling
• CPC Class Codes: H04L 49/3054 : Auto-negotiation, e.g. access control between switch gigabit interface connector [GBIC] and link
• CPC Class Codes: H04L 49/3081 : ATM peripheral units, e.g. policing, insertion or extraction
• CPC Class Codes: H04L 49/351 : for local area network [LAN], e.g. Ethernet switches
• CPC Class Codes: H04L 49/352 : Gigabit ethernet switching [GBPS]
• CPC Class Codes: H04L 49/354 : for supporting virtual local area networks [VLAN]
• CPC Class Codes: H04L 49/45 : Arrangements for providing or supporting expansion
• CPC Class Codes: H04L 49/602 : Multilayer or multiprotocol switching, e.g. IP switching
• CPC Class Codes: H04L 49/90 : Buffering arrangements
• CPC Class Codes: H04L 49/901 : using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9047 : including multiple buffers, e.g. buffer pools
• CPC Class Codes: H04L 49/9057 : Arrangements for supporting packet reassembly or resequencing
• CPC Class Codes: H04L 49/9073 : Early interruption upon arrival of a fraction of a packet
• CPC Class Codes: H04L 67/10 : in which an application is distributed across nodes in the network software deployment G06F8/60; multiprogramming arrangements G06F9/46
• CPC Class Codes: H04L 69/14 : Multichannel or multilink protocols
• CPC Class Codes: H04L 69/16 : Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
• CPC Class Codes: H04L 69/161 : Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields

Abstract

A network switch for network communications includes a first data port interface, wherein the first data port interface supports a plurality of data ports for transmitting and receiving data at a first data rate. The network switch also includes a second data port interface, wherein the second data port interface supports a plurality of data ports for transmitting and receiving data at a second data rate, along with a third data port interface for transmitting and receiving data at a third data rate. A CPU interface is provided and configured to communicate with a CPU. The switch includes a first, second and third internal memory communicating with the first, second and third data port interface. A first and second memory management unit for communicating data and to control access to and from the second internal memory, are also provided. A communication channel is provided for communicating data and messaging information.

Claims

1. A network switch for network communications, said network switch comprising:

a communication channel comprising;

a cell channel configured to communicate data from at least one packet between a first data port interface, a second data port interface, a third data port interface, a first internal memory, and a first memory management unit;

a protocol channel configured to communicate a message header defining a message type of the at least one packet between the first data port interface, the second data port interface, the third data port interface, the first internal memory, and the first memory management unit, the message type controlling the data communicated on the cell channel; and

a sideband channel configured to communicate status information, independently of the cell channel and the protocol channel, associated with the first data port interface, the second data port interface, the third data port interface, the first internal memory, and the first memory management unit;

the first memory management unit configured to direct data from one of said first data port interface, said second data port interface, and said third data port interface to one of said first internal memory and an external memory interface; and

an appending unit configured to append a module identification header comprising an identification bitmap that identifies other network switches to which the data packet should be sent via the third data port interface.

2. The network switch of claim 1, further comprising:

a second memory management unit configured to monitor the communication channel and receive data packets from the communication channel,

wherein the data packets are destined for the third data port interface from one of the first data port interface and the second data port interface.

3. The network switch of claim 1, wherein the module identification header appended to the data packet by the appending unit includes mirroring information which identifies a destination port on a remote network switch.

4. The network switch of claim 1, wherein the module identification header includes data identifying a class-of-service priority for the data packet.

5. The network switch of claim 1, wherein the module identification header includes data which identifies the network switch as a source network switch for the data packet.

6. The network switch of claim 1, wherein said third data port includes a plurality of tables.

7. The network switch of claim 6, wherein the plurality of tables include at least one of a programmable virtual local area network (VLAN) table, a multicast table, an Internet Protocol (IP) multicast table, a trunk group bitmap table, a priority-to-class-of-service queue mapping table, and a port-to-class-of-service mapping table.

8. The network switch of claim 1, wherein:

said first data port interface is configured to support a plurality of data ports transmitting and receiving data in accordance with an Ethernet standard,

said second data port interface supports a plurality of data ports transmitting and receiving data in accordance with the Ethernet standard, and

wherein said data port interface is a high-performance interface for communicating with other network switches in a stacked configuration.

9. The network switch of claim 8, wherein said third data port interface contains a single input-output port.

10. The network switch of claim 1, wherein said first data port interface and said second data port interface include a packet sliding unit for slicing variable length packets into a plurality of equal length cells.

11. The network switch of claim 1, wherein said first data port interface, second data port interface, third data port interface, first internal memory, first memory management unit, and said communication channel are integrated on a single application specific integrated circuit (ASIC) chip.

12. The network switch of claim 1, further comprising a second internal memory and a second memory management unit which are part of the third data port interface.

13. The network switch of claim 1, further comprising:

a second memory management unit configured to control access to a second internal memory, the second memory management unit comprising a scheduler, the scheduler being in communication with the second internal memory configured to control forwarding of packets out of the network switch from the second internal memory.

14. The network switch of claim 13, further comprising an arbiter, in communication with the scheduler, configured to control access to a communication line to which the data port interfaces are connected.

15. The network switch of claim 1, further comprising:

a stripping unit configured to strip a module header from packets that are switched out of the network switch.

16. The network switch of claim 1, wherein the cell channel is configured to communicate only data from the at least one packet between the first data port interface, the second data port interface, the third data port interface, the first internal memory, and the first memory management unit.

17. The network switch of claim 1, wherein the protocol channel is configured to lock an opcode of the at least one packet with a predetermined cell block of the data communicated through the cell channel.

18. The network switch of claim 1, wherein the sideband channel is configured to communicate an address resolution logic (ARL) insert message, the ARL insert message instructing ARL/L3 tables to learn a new address included in the ARL insert message.