Method of and circuit for oversampling a signal in an integrated circuit

• US 7,782,990 B1
• Filed: 09/27/2006
• Issued: 08/24/2010
• Est. Priority Date: 09/27/2006
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Snow, John F.
• Primary Examiner(s): Payne; David C
• Assistant Examiner(s): Panwalkar; Vineeta S
• Application Number:
  US11/527,880
• Time in Patent Office: 1,427 Days
• Field of Search: 375/354, 375/355, 375/326, 375373-376, 327/141, 327/144, 327145-163
• US Class Current: 375/355
• CPC Class Codes: H03L 7/08 Details of the phase-locked loop
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

A method of oversampling a signal in an integrated circuit is disclosed. The method comprises receiving a reference clock signal; generating at least one delayed clock signal, each having a different phase; receiving an input data signal; generating at least one delayed data signal based upon the input data signal; and generating a plurality of phase-shifted output signals, each phase-shifted output signal being based upon a different combination of a clock signal and a data signal. A circuit for oversampling a signal in an integrated circuit is also disclosed.

Claims

1. A method of oversampling a signal in an integrated circuit, the method comprising:

receiving a reference clock signal;

generating at least one delayed clock signal based upon the reference clock signal, each delayed clock signal having a different phase;

receiving an input data signal;

generating at least one delayed data signal based upon the input data signal; and

generating a plurality of phase-shifted output signals, each phase-shifted output signal being based upon a different combination of a clock signal, selected from the at least one delayed clock signal and the reference clock signal, and a data signal, selected from the at least one delayed data signal and the input data signal, wherein each clock signal of the at least one delayed clock signal and the reference clock signal is used to generate more than one phase-shifted output signal of the plurality of phase-shifted output signals and wherein each data signal of the at least one delayed data signal and the input data signal is used to generate more than one phase-shifted output signal of the plurality of phase-shifted output signals, and wherein each clock signal of the at least one delayed clock signal and the reference clock signal is used with each data signal of the at least one delayed data signal and the input data signal to generate the plurality of phase-shifted output signals.

2. The method of claim 1 wherein generating the at least one delayed clock signal comprises generating a plurality of delayed clock signals having different phases.

3. The method of claim 2 wherein generating the plurality of delayed clock signals having different phases comprises generating a first delayed clock signal by way of a first delay element and generating a second delayed clock signal by way of a second delay element.

4. The method of claim 1 wherein generating the at least one delayed data signal based upon the input data signal comprises generating a plurality of delayed data signals.

5. The method of claim 4 wherein generating the plurality of delayed data signals comprises generating a first delayed data signal by way of a first delay element and a generating a second delayed data signal by way of a second delay element.

6. The method of claim 1 wherein generating a plurality of phase-shifted output signals comprises receiving a different combination of a delayed clock signal and a delayed data signal at each register of a plurality of registers.

7. A method of oversampling a signal in an integrated circuit, the method comprising:

receiving a reference clock signal;

coupling the reference clock signal to a clock manager to generate at least one clock signal having a different phase;

receiving an input data signal;

coupling the input data signal to at least one delay element to generate at least one delayed data signal based upon the input data signal; and

generating a plurality of phase-shifted output signals, each phase-shifted output signal being based upon a different combination of a clock signal, selected from the at least one clock signal and the reference clock signal, and a data signal, selected from the at least one delayed data signal and the input data signal, wherein each clock signal of the at least one clock signal having a different phase and the reference clock signal is used to generate more than one phase-shifted output signal of the plurality of phase-shifted output signals and wherein each data signal of the at least one delayed data signal and the input data signal is used to generate more than one phase-shifted output signal of the plurality of phase-shifted output signals, and wherein each clock signal of the at least one delayed clock signal and the reference clock signal is used with each data signal of the at least one delayed data signal and the input data signal to generate the plurality of phase-shifted output signals.

8. The method of claim 7 wherein coupling the reference clock signal to a clock manager comprises generating a plurality of clock signals having different phases.

9. The method of claim 8 wherein coupling the input data signal to at least one delay element comprises coupling the input data signal to a plurality of delay elements.

10. The method of claim 9 wherein generating the plurality of phase-shifted output signals comprises receiving a different combination of a clock signal and a data signal at each register of a plurality of registers.

11. The method of claim 10 wherein generating a plurality of clock signals having different phases comprises generating a plurality of clock signals which are evenly spaced.

12. The method of claim 9 wherein coupling the input data signal to a plurality of delay elements comprises coupling the input data signal to a first delay element which is set to provide no delay.

13. The method of claim 9 wherein coupling the input data signal to a plurality of delay elements comprises providing delay elements in input/output blocks of a programmable logic device.

14. A circuit for oversampling a signal in an integrated circuit, the circuit comprising:

a first input coupled to receive a reference clock signal;

a first circuit receiving the reference clock signal and generating at least one delayed clock signal;

a second input coupled to receive an input data signal;

a second circuit receiving the input data signal and generating at least one delayed data signal; and

a plurality of registers coupled to the first circuit and the second circuit, each register receiving a different combination of a clock signal, selected from the at least one delayed clock signal and the reference clock signal, and a data signal, selected from the at least one delayed data signal and the input data signal, to generate an output signal having a different phase, wherein each clock signal of the at least one delayed clock signal and the reference clock signal is coupled to more than one register of the plurality of registers and wherein each data signal of the at least one delayed data signal and the input data signal is coupled to more than one register of the plurality of registers and wherein each clock signal of the at least one delayed clock signal and the reference clock signal is used with each data signal of the at least one delayed data signal and the input data signal to generate a plurality of phase-shifted output signals.

15. The circuit of claim 14 wherein the second circuit comprises a delay element implemented in programmable logic of a programmable logic device.

16. The circuit of claim 15 wherein the first circuit comprises a clock manager generating a plurality of delayed clock signals having different phases.

17. The circuit of claim 16 further comprising a second delay element receiving the input data signal and generating a second delayed data signal.

18. The circuit of claim 14 wherein the first circuit comprises a circuit selected from a group consisting of a delay element, a PLL, a DLL, and a digital clock manager.

19. The circuit of claim 14 further comprising a third circuit generating a second delayed clock signal.