Fractionally related multirate signal processor and method
First Claim
1. A multirate processing circuit, comprisinga resampling filter accepting a sampled input signal sampled with a first clock rate, wherein the multirate processing circuit uses less memory to implement fewer delay line stages when the input signal is processed by circuitry operating at a second clock rate than when the input signal is processed by circuitry operating at the first clock rate, the resampling filter filtering the sampled input signal to remove spectral components above a spectral bandwidth of the second clock rate, the resampling filter producing a band limited sampled signal sampled at the first clock rate;
- a discrete time processor operating with a clock rate that is an integer power of two multiple of the first clock rate, the discrete time processor communicatively coupled to the resampling filter to receive the band limited sampled signal, the discrete time processor adapted to process samples of the band limited sampled signal by excluding selected samples of the band limited sampled signal from the processing so as to effectively perform discrete time processing of the band limited sampled signal at the integer power of two multiple of the second clock rate; and
a subsequent discrete time processor, communicatively coupled to an output of the discrete time processor, the subsequent discrete time processor processing, at an integer power of two multiple of the first clock rate, samples produced at the output of the discrete time processor, the subsequent discrete time processor further excluding from the processing selected samples so as to effectively perform discrete time processing of the samples produced at the output of the discrete time processor at the integer power of two multiple of the second clock rate.
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Abstract
A multirate processing circuit (100) with a resampling filter (106) to accept a sampled input signal (104) sampled with a first clock rate and to filter the sampled input signal to remove spectral components above a spectral bandwidth of a second clock rate. The sampled input signal represents a signal that is more efficiently processed at the second clock rate, which is fractionally related to the first clock rate. The multirate processing circuit (100) also has a discrete time processor (108) that receives the resampling filter output (130) and processes that output at an integer power of two multiple of the first clock rate. The discrete time processor (108) further excludes selected samples from the processing so as to effectively perform discrete time processing of the resampling filter output (130) at the integer power of two multiple of the second clock rate.
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Citations
20 Claims
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1. A multirate processing circuit, comprising
a resampling filter accepting a sampled input signal sampled with a first clock rate, wherein the multirate processing circuit uses less memory to implement fewer delay line stages when the input signal is processed by circuitry operating at a second clock rate than when the input signal is processed by circuitry operating at the first clock rate, the resampling filter filtering the sampled input signal to remove spectral components above a spectral bandwidth of the second clock rate, the resampling filter producing a band limited sampled signal sampled at the first clock rate; -
a discrete time processor operating with a clock rate that is an integer power of two multiple of the first clock rate, the discrete time processor communicatively coupled to the resampling filter to receive the band limited sampled signal, the discrete time processor adapted to process samples of the band limited sampled signal by excluding selected samples of the band limited sampled signal from the processing so as to effectively perform discrete time processing of the band limited sampled signal at the integer power of two multiple of the second clock rate; and a subsequent discrete time processor, communicatively coupled to an output of the discrete time processor, the subsequent discrete time processor processing, at an integer power of two multiple of the first clock rate, samples produced at the output of the discrete time processor, the subsequent discrete time processor further excluding from the processing selected samples so as to effectively perform discrete time processing of the samples produced at the output of the discrete time processor at the integer power of two multiple of the second clock rate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method with a multirate processing circuit including a resampling filter and a discrete time processor, for processing discrete time signals, the method comprising:
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accepting a sampled input signal sampled with a first clock rate, wherein the multirate processing circuit uses less memory to implement fewer delay line stages when the input signal is processed by circuitry operating at a second clock rate than when the input signal is processed by circuitry operating at the first clock rate; filtering the sampled input signal to remove spectral components above a spectral bandwidth of the second clock rate to produce a band-limited sampled signal sampled at the first clock rate; processing, with a clock rate that is an integer power of two multiple of the first clock rate, samples of the band-limited sampled signal while excluding from the processing selected samples of the band-limited sampled signal so as to effectively perform discrete time processing of the band-limited sampled signal at the integer power of two multiple of the second clock rate; and providing synchronization signals indicating occurrences of the selected samples to the resampling filter and the discrete time processor. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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18. A signal processing circuit, comprising:
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at least one of a radio frequency receiver adapted to selectively receiving a radio frequency signal and producing a downconverted and conditioned signal and a radio frequency transmitter adapted to selectively generation a radio frequency signals for transmission; an analog to digital converter, communicatively coupled to the radio frequency receiver, the analog to digital converter accepting the downconverted and conditioned signal and producing a sampled input signal sampled with a first clock rate, wherein the signal processing circuit uses less memory to implement fewer delay line stages when the input signal is processed by circuitry operating at a second clock rate than when the input signal is processed by circuitry operating at the first clock rate, the second clock rate being different from and fractionally related to the first clock rate; a resampling filter, communicatively coupled to the analog to digital converter, the resampling filter accepting the sampled input signal, the resampling filter filtering the sampled input signal to remove spectral components above a spectral bandwidth of the second clock rate, the resampling filter producing a band limited sampled signal sampled at the first clock rate; and a discrete time processor operating with a clock rate that is an integer power of two multiple of the first clock rate, the discrete time processor communicatively coupled to the resampling filter to receive the band limited sampled signal, the discrete time processor adapted to process samples of the band limited sampled signal by excluding selected samples of the band limited sampled signal from the processing so as to effectively perform discrete time processing of the band limited sampled signal at the integer power of two multiple of the second clock rate. - View Dependent Claims (19, 20)
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Specification