Fractionally related multirate signal processor and method

• US 7,782,991 B2
• Filed: 01/09/2007
• Issued: 08/24/2010
• Est. Priority Date: 01/09/2007
• Status: Expired due to Fees

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Rahman, Mahibur, Quiroga, Emilio J., Sobchak, Charles Leroy
• Primary Examiner(s): Payne, David C
• Assistant Examiner(s): Stevens, Brian J
• Application Number:
  US11/621,387
• Publication Number:
  US 20080165907A1
• Time in Patent Office: 1,323 Days
• Field of Search: 375/355, 375/373, 375/354, 375/371
• US Class Current: 375/355
• CPC Class Codes: H03H 17/0628 the input and output signals being derived from two separate clocks, i.e. asynchronous sample rate conversion
• CPC Class Codes: H03H 17/0685 the ratio being rational
• CPC Class Codes: H04L 7/0029 interpolation of received data signal

Abstract

A multirate processing circuit (100) with a resampling filter (106) to accept a sampled input signal (104) sampled with a first clock rate and to filter the sampled input signal to remove spectral components above a spectral bandwidth of a second clock rate. The sampled input signal represents a signal that is more efficiently processed at the second clock rate, which is fractionally related to the first clock rate. The multirate processing circuit (100) also has a discrete time processor (108) that receives the resampling filter output (130) and processes that output at an integer power of two multiple of the first clock rate. The discrete time processor (108) further excludes selected samples from the processing so as to effectively perform discrete time processing of the resampling filter output (130) at the integer power of two multiple of the second clock rate.

Claims

1. A multirate processing circuit, comprising

a resampling filter accepting a sampled input signal sampled with a first clock rate, wherein the multirate processing circuit uses less memory to implement fewer delay line stages when the input signal is processed by circuitry operating at a second clock rate than when the input signal is processed by circuitry operating at the first clock rate, the resampling filter filtering the sampled input signal to remove spectral components above a spectral bandwidth of the second clock rate, the resampling filter producing a band limited sampled signal sampled at the first clock rate;

a discrete time processor operating with a clock rate that is an integer power of two multiple of the first clock rate, the discrete time processor communicatively coupled to the resampling filter to receive the band limited sampled signal, the discrete time processor adapted to process samples of the band limited sampled signal by excluding selected samples of the band limited sampled signal from the processing so as to effectively perform discrete time processing of the band limited sampled signal at the integer power of two multiple of the second clock rate; and

a subsequent discrete time processor, communicatively coupled to an output of the discrete time processor, the subsequent discrete time processor processing, at an integer power of two multiple of the first clock rate, samples produced at the output of the discrete time processor, the subsequent discrete time processor further excluding from the processing selected samples so as to effectively perform discrete time processing of the samples produced at the output of the discrete time processor at the integer power of two multiple of the second clock rate.

2. The multirate processing circuit of claim 1, wherein the second clock rate is not a multiple of the first clock rate and wherein the second clock rate is neither a positive integer power of two nor a negative integer power of two.

3. The multirate processing circuit of claim 1, wherein the second clock rate is an integer multiple of a periodicity within the sampled input signal.

4. The multirate processing circuit of claim 3, wherein the sampled input signal comprises a digitally modulated communications signal and wherein the second clock rate is an integer multiple of a symbol rate of the digitally modulated communications signal.

5. The multirate processing circuit of claim 1, further comprising a sampling algorithm controller, communicatively coupled to the resampling filter and the discrete time processor, the sampling algorithm controller adapted to provide synchronization signals indicating occurrences of the selected samples to the resampling filter and the discrete time processor.

6. The multirate processing circuit of claim 5, further comprising an output buffer, communicatively coupled to the resampling filter and the sampling algorithm controller, the output buffer adapted to removing the selected samples from the band limited sampled signal to produce a downsampled output signal at an integer power of two multiple of the second clock rate.

7. The multirate processing circuit of claim 6, wherein the output buffer circuitry is communicatively coupled to the resampling filter through at least one intermediate processing stage.

8. The multirate processing circuit of claim 6, wherein the output buffer circuitry is controlled by a data clock operating at the first clock frequency.

9. The multirate processing circuit of claim 5, wherein the discrete time processor comprises a finite impulse response filter, the finite impulse response filter adapted to exclude, in response to receiving the synchronization signals, the selected samples from the processing performed by the finite impulse response filter.

10. The multirate processing circuit of claim 9, wherein the finite impulse response filter comprises a multiple tap delay line providing a plurality of scaled delay line tap outputs to a summer, the multiple tap delay line adapted to selectively withhold, in response to the synchronization signals, providing at least one delay line tap output to the summer.

11. A method with a multirate processing circuit including a resampling filter and a discrete time processor, for processing discrete time signals, the method comprising:

accepting a sampled input signal sampled with a first clock rate, wherein the multirate processing circuit uses less memory to implement fewer delay line stages when the input signal is processed by circuitry operating at a second clock rate than when the input signal is processed by circuitry operating at the first clock rate;

filtering the sampled input signal to remove spectral components above a spectral bandwidth of the second clock rate to produce a band-limited sampled signal sampled at the first clock rate;

processing, with a clock rate that is an integer power of two multiple of the first clock rate, samples of the band-limited sampled signal while excluding from the processing selected samples of the band-limited sampled signal so as to effectively perform discrete time processing of the band-limited sampled signal at the integer power of two multiple of the second clock rate; and

providing synchronization signals indicating occurrences of the selected samples to the resampling filter and the discrete time processor.

12. The method of claim 11, wherein the second clock rate is not related to the first clock rate by a multiple of 2ⁿ or ½

ⁿ.

13. The method of claim 11, wherein the second clock rate is an integer multiple of a periodicity within the sampled input signal.

14. The method of claim 13, wherein the sampled input signal comprises a digitally modulated communications signal and wherein the second clock rate is an integer multiple of a symbol rate of the digitally modulated communications signal.

15. The method of claim 11, further comprising preliminarily processing, prior to the processing, the band limited sampled signal with at least one intermediate processing stage.

16. The method of claim 11, wherein the processing comprises filtering with a finite impulse response filter, the finite impulse response filter adapted to exclude, in response to receiving the synchronization signals, the selected samples from the processing.

17. The method of claim 16, wherein the finite impulse response filter comprises a multiple tap delay line providing a plurality of scaled delay line tap outputs to a summer, the multiple tap delay line adapted to selectively withhold, in response to the synchronization signals, providing at least one delay line tap output to the summer.

18. A signal processing circuit, comprising:

at least one of a radio frequency receiver adapted to selectively receiving a radio frequency signal and producing a downconverted and conditioned signal and a radio frequency transmitter adapted to selectively generation a radio frequency signals for transmission;

an analog to digital converter, communicatively coupled to the radio frequency receiver, the analog to digital converter accepting the downconverted and conditioned signal and producing a sampled input signal sampled with a first clock rate, wherein the signal processing circuit uses less memory to implement fewer delay line stages when the input signal is processed by circuitry operating at a second clock rate than when the input signal is processed by circuitry operating at the first clock rate, the second clock rate being different from and fractionally related to the first clock rate;

a resampling filter, communicatively coupled to the analog to digital converter, the resampling filter accepting the sampled input signal, the resampling filter filtering the sampled input signal to remove spectral components above a spectral bandwidth of the second clock rate, the resampling filter producing a band limited sampled signal sampled at the first clock rate; and

a discrete time processor operating with a clock rate that is an integer power of two multiple of the first clock rate, the discrete time processor communicatively coupled to the resampling filter to receive the band limited sampled signal, the discrete time processor adapted to process samples of the band limited sampled signal by excluding selected samples of the band limited sampled signal from the processing so as to effectively perform discrete time processing of the band limited sampled signal at the integer power of two multiple of the second clock rate.

19. The signal processing circuit of claim 18, including a subsequent discrete time processor, communicatively coupled to an output of the discrete time processor, the subsequent discrete time processor processing, at an integer power of two multiple of the first clock rate, samples produced at the output of the discrete time processor, the subsequent discrete time processor further excluding from the processing selected samples so as to effectively perform discrete time processing of the samples produced at the output of the discrete time processor at the integer power of two multiple of the second clock rate.

20. The signal processing circuit of claim 18, including a sampling frequency control algorithm controller, communicatively coupled to the radio frequency receiver, for providing synchronization signals that indicate occurrences of the selected samples.