Fast flag generation

• US 7,783,692 B1
• Filed: 07/05/2005
• Issued: 08/24/2010
• Est. Priority Date: 07/05/2005
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Tan, Teik-Chung, Wong, Wing-Shek, Tuuk, Michael E.
• Primary Examiner(s): Bullock, Jr.; Lewis A
• Assistant Examiner(s): YAARY, MICHAEL D
• Application Number:
  US11/175,083
• Time in Patent Office: 1,876 Days
• Field of Search: 708200-209
• US Class Current: 708/209
• CPC Class Codes: G06F 5/01 for shifting, e.g. justifying, scaling, normalising digital stores in which the information is moved stepwise, e.g. shift-registers G11C19/00; digital stores in which the information circulates G11C21/00

Abstract

A method and circuit for fast flag generation. The circuit is coupled to receive data to be shifted, the data including a first plurality of bits. A shift count value (including a second plurality of bits) is also received by the circuit, as well as an indication of a direction the data is to be shifted. Based on the shift count value and the indication of direction, the position of a bit within the data is determined. The bit is then output as a flag bit.

Claims

1. A method comprising:

receiving, in a processor core, data to be shifted, wherein the data includes a first plurality of bits;

receiving a shift count value including a second plurality of bits, wherein the shift count value represents a number of bit positions the data is to be shifted;

receiving an indication of a direction the data is to be shifted;

determining, by way of circuitry within the processor core, a bit position of a flag bit within the first plurality of bits based on the shift count value and the direction, wherein, when the data is to be shifted in a leftward direction, the bit position of the flag bit is determined by inverting the second plurality of bits of the shift count and adding a value of binary 1, and wherein, when the data is to be shifted a rightward direction, the bit position of the flag bit is determined by subtracting a value of binary 1 from the shift count value; and

outputting the flag bit.

2. The method as recited in claim 1, wherein the first plurality of bits has a maximum number of bits corresponding to a maximum operand size.

3. The method as recited in claim 2 further comprising masking one or more higher order bits of an indication of the bit position when an operand size of the data to be shifted is less than the maximum operand size.

4. The method as recited in claim 1 further comprising shifting the data.

5. The method as recited in claim 4, wherein said receiving data, said receiving a shift count value, said receiving an indication, said determining, and said outputting is performed in parallel with said shifting the data.

6. The method as recited in claim 1, wherein the flag bit is a carry flag.

7. A circuit comprising:

a plurality of selection circuits, wherein a subset of the plurality of selection circuits is coupled to receive data to be shifted, wherein the data comprises a first plurality of bits; and

a position circuit, wherein the position circuit is coupled to receive a shift count value comprising a second plurality of bits, the shift count value representing a number of bit positions the data is to be shifted, and an indication of a direction the data is to be shifted;

wherein the position circuit is configured to;

determine a bit position of the flag bit by inverting the shift count value and adding a value of binary 1 if the data is to be shifted in a leftward direction; and

determine the bit portion of the flag bit by subtracting a value of binary 1 from the shift count value if the data is to be shifted in a rightward direction; and

wherein the selection circuits are coupled to receive an indication of the bit position from the position circuit and configured to select and output the flag bit based on the indication of the bit position, wherein the indication of the bit position comprises a third plurality of bits.

8. The circuit as recited in claim 7, wherein the first plurality of bits has a maximum number of bits corresponding to a maximum operand size.

9. The circuit as recited in claim 8 further comprising a masking circuit configured to mask one or more higher order bits of the indication of the bit position when an operand size of the data to be shifted is less than the maximum operand size.

10. The circuit as recited in claim 7, wherein the circuit further includes a shifter coupled to receive the data.

11. The circuit as recited in claim 10, wherein the shifter is configured to operate in parallel with the position circuit and the plurality of selection circuits.

12. The circuit as recited in claim 7, wherein the flag bit is a carry flag.

13. The circuit as recited in claim 7, wherein each of the plurality of selection circuits is a multiplexer.

14. The circuit as recited in claim 13, wherein selection signals provided to each of the plurality of multiplexers include one or more of the third plurality of bits.

15. The circuit as recited in claim 7, wherein the circuit is implemented in an execution path of a processor.

16. A circuit comprising:

a plurality of multiplexers, wherein each of a subset of the plurality of multiplexers is coupled to receive a subset of a first plurality of bits, the first plurality of bits comprising data to be shifted, and wherein in one of the plurality of multiplexers is coupled to receive an output provided by each of the subset of the plurality of multiplexers;

a position circuit including;

a first logic circuit, wherein the first logic circuit is coupled to receive a shift count value comprising a second plurality of bits, wherein the first logic circuit is configured to invert the second plurality of bits and add a value of binary 1;

a second logic circuit coupled to receive the shift count value, wherein the second logic circuit is configured to subtract a value of binary 1 from the second plurality of bits; and

a selection circuit, wherein the selection circuit is configured to receive a direction signal indicating if the first plurality of bits is to be shifted in a leftward or a rightward direction, and wherein, if the data is to be shifted leftward, select an output provided by the first logic circuit, and wherein, if the data is to be shifted rightward, select an output from the second logic circuit, and wherein an output from the selection circuit comprises a third plurality of bits; and

a masking circuit, wherein the masking circuit is coupled to receive a higher order subset of the third plurality of bits, and further configured to mask one or more of the subset of the third plurality of bits if an operand size of the data to be shifted is less than a maximum operand size;

wherein the subset of multiplexers is coupled to receive, as selection signals, a lower order subset of the third plurality of bits and the one of the plurality of multiplexers is configured to receive as selection signal outputs from the masking circuit, and wherein, based on the selection signals received, one of the first plurality of bits is allowed to propagate through the plurality of multiplexers and is output as a carry flag.

17. The circuit as recited in claim 16 further comprising a shifter circuit, wherein the shifter circuit is coupled to receive the data to be shifted, and further configured to shift the data a number of bit positions indicated by the shift count value in the direction indicated by the direction signal.