Multi-node configuration of processor cards connected via processor fabrics

• US 7,783,813 B2
• Filed: 06/14/2007
• Issued: 08/24/2010
• Est. Priority Date: 06/14/2007
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Verdoorn, William Garrett Jr., Walls, Andrew Dale
• Primary Examiner(s): Tsai; Henry W. H.
• Assistant Examiner(s): TSENG, CHENG YUAN
• Application Number:
  US11/763,411
• Publication Number:
  US 20080313369A1
• Time in Patent Office: 1,167 Days
• Field of Search: 361/694, 361/695, 709/201, 710/22, 710/30, 710/62, 710/104, 710/110, 710/269, 710/301, 710/302, 710/305, 710/316, 711/147, 714/100, 714/2
• US Class Current: 710/305
• CPC Class Codes: G06F 15/16 Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs coordinating program control therefor G06F9/52; in regulating and control system G05B

Abstract

Provided is a system comprising a first node comprising a plurality of processor cards each including a processor fabric, wherein the processor cards in the first node connect via their processor fabrics; a second node comprising a plurality of processor cards each including a processor fabric, wherein the processor cards in the second node connect via their processor fabrics; and a plurality of communication interfaces, wherein each interface connects one processor card in the second node to one processor card in the first node to enable communication between the connected processor cards to coordinate processor operations between the connected processor cards in the first and second nodes.

Claims

1. A system, comprising:

a first midplane having a first and second processor cards, each of the first and second processor cards having a processor fabric;

a second midplane having a third and fourth processor cards, each of the third and fourth processor cards having a processor fabric;

a first node comprising the first and third processor cards in the first and second midplanes, wherein the processor cards in the first node connect via their processor fabrics;

a second node comprising the second and fourth processor cards in the first and second midplanes wherein the processor cards in the second node connect via their processor fabrics;

a first cable connecting the processor fabrics of the processor cards in the first node;

a second cable connecting the processor fabrics of the processor cards in the second node; and

a first and second communication interfaces, wherein the first communication interface connects the first and second processor cards and wherein the second communication interface connects the third and fourth processor cards, wherein the first and second communication interfaces enable communication between the connected processor cards in the first and second nodes to coordinate processor operations between the connected processor cards in the first and second nodes, wherein the communication interfaces and processor fabrics utilize different technologies, wherein the processor cards in each of the first and second nodes that communicate over their processor fabrics function as first and second symmetrical multi-processors,

wherein each processor card includes management code executed by the processor card to perform;

configuring the first node comprising the first and third processor cards in the first and second midplanes; and

configuring the second node comprising the second and fourth processor cards in the first and second midplanes.

5. The system of claim 1, wherein the first, second, third, and fourth processor cards in different of the first and second nodes do not communicate with each other using processor fabric technology.

6. The system of claim 1, wherein each midplane is included within a storage server.

7. The system of claim 1 wherein each midplane includes an Input/Output (I/O) adaptor enabling communication with an external device, wherein each processor card in each midplane is connected to the I/O adaptor on the midplane using a communication interface different from the processor fabric.

2. A system, comprising:

a first midplane including;

a first and second processor cards, wherein each processor card includes a processor fabric; and

a first communication interface connecting the first and second processor cards to enable communication between the first and second processor cards; and

a second midplane including;

a third and fourth processor cards, wherein each processor card includes a processor fabric, wherein the first and third processor cards connect via their processor fabrics and wherein the second and fourth processor cards connect via their processor fabrics; and

a second communication interface connecting the third and fourth processor cards to enable communication between the third and fourth processor cards, wherein the communication interfaces and processor fabrics utilize different technologies, wherein the connected first and third processor cards and connected second and fourth processor cards function as first and second symmetrical multi-processors;

a first cable connecting the processor fabrics of the first and third processor cards;

a second cable connecting the processor fabrics of the second and fourth processor cards;

wherein each processor card includes management code executed by the processor card to perform;

configuring a first node comprising the first and third processor cards in the first and second midplanes; and

configuring a second node comprising the second and fourth processor cards in the first and second midplanes.

8. The system of claim 2, wherein each midplane is included within a storage server.

9. The system of claim 8, wherein each midplane includes an Input/Output (I/O) adaptor enabling communication with an external device, wherein each processor card in each midplane is connected to the I/O adaptor on the midplane using a communication interface different from the processor fabric.

3. A method, comprising:

configuring a first node comprising a first processor card in a first midplane and a third processor card in a second midplane, wherein each of the first and third processor cards has a processor fabric and wherein the first and third processor cards connect via their processor fabrics;

configuring a second node comprising a second processor card in a first midplane and a fourth processor card in a second midplane, wherein each of the second and fourth processor cards has a processor fabric, wherein the second and fourth processor cards connect via their processor fabrics, wherein each of the first and second processor cards include management code to configure the first and second nodes;

configuring a first and second communication interfaces, wherein the first communication interface connects the first and second processor cards and wherein the second communication interface connects the third and fourth processor cards, wherein the first and second communication interfaces enable communication between the connected processor cards in the first and second nodes to coordinate processor card operations between the connected processor cards in the first and second nodes, wherein the communication interfaces and processor fabrics utilize different technologies, wherein configuring the first and second nodes and the processor fabrics comprises configuring the first and second nodes to function as a first and second symmetrical multi-processors, respectively.

4. An article of manufacture comprising a computer readable storage medium storing code implemented in processor cards each having a processor fabric and coupled to one of a plurality of communication interfaces, wherein the code causes operations to be performed, the operations comprise:

configuring a first node comprising a first processor card in a first midplane and a third processor card in a second midplane, wherein each of the first and third processor cards has a processor fabric wherein the first and third processor cards connect via their processor fabrics;

configuring a second node comprising a second processor card in a first midplane and a fourth processor card in a second midplane, wherein each of the second and fourth processor cards has a processor fabric, wherein the second and fourth processor connect via their processor fabrics, wherein each of the first and second processor cards include code to configure the first and second nodes;

configuring a first and second communication interfaces, wherein the first communication interface connects the first and second processor cards and wherein the second communication interface connects the third and fourth processor cards, wherein the first and second communication interfaces enable communication between the connected processor cards in the first and second nodes to coordinate processor card operations between the connected processor cards in the first and second nodes, wherein the communication interfaces and processor fabrics utilize different technologies, wherein configuring the first and second nodes and the processor fabrics comprises configuring the first and second nodes to function as a first and second symmetrical multi-processors, respectively.