Packet-switched split computer having disassociated peripheral controller and plural data buses

• US 7,783,820 B2
• Filed: 12/21/2006
• Issued: 08/24/2010
• Est. Priority Date: 12/30/2005
• Status: Expired due to Fees

• Current Assignee: Avocent Corporation (Vertiv Holdings Co.)
• Original Assignee: Avocent Corporation (Vertiv Holdings Co.)
• Inventors: Luterman, Greg, Shelton, Gary Warren
• Primary Examiner(s): PHAN, RAYMOND NGAN
• Application Number:
  US11/642,641
• Publication Number:
  US 20070283181A1
• Time in Patent Office: 1,342 Days
• Field of Search: 710300-307, 710310-315, 710104-107, 710123-129, 710 62- 65, 710 72- 73, 710/22, 713/400, 370/260, 370389-392
• US Class Current: 710/314
• CPC Class Codes: G06F 13/4045 where the bus bridge performs an extender function
• CPC Class Codes: H04L 12/66 Arrangements for connecting between networks having differing types of switching systems, e.g. gateways

Abstract

A network interface is described in which a single computer bus is split over a long distance into two or more intercommunicating buses. On one bus, processing and applications are provided and on the other remote bus, peripheral and local controllers are provided. The buses communicate through a series of: bridge, a first communications controller, a second communications controller, and bridge. Between the communications controllers, a communication path provides long distance communication via a packet-switched network.

Claims

1. A remote-distance communications interface between a processor and physically disassociated peripheral controllers, comprising:

a first data bus onto which the processor communicates;

a second data bus, physically disassociated from the first data bus, onto which the disassociated peripheral controllers communicate;

a bus interface coupling the first and second data buses to organize communication between said processor and said disassociated peripheral controllers and including at least one clock domain barrier between said first and second data buses;

a first communications controller coupled to the first data bus; and

a second communications controller coupled to the second data bus, wherein the communication between the first and second communications controllers is carried by packet-switch-based communications passing through at least one router.

2. An interface according to claim 1, wherein the bus interface includes a host interface coupled to the first data bus and a terminal interface coupled to the second data bus.

3. An interface according to claim 1, wherein the bus interface further includes a second clock domain barrier between said first and second data buses.

4. An interface according to claim 1, wherein the packet-switch-based communications comprise IP-compatible, packet-switched communications.

5. An interface according to claim 1, wherein the packet-switch-based communications comprise UDP-compatible, packet-switched communications.

6. An interface according to claim 1, wherein the packet-switch-based communications comprise ATM-switch-based communications.

7. An interface according to claim 2, wherein:

the host interface further includes a first bridge coupled to the first data bus, and

the terminal interface further includes a second bridge coupled to the second data bus.

8. An interface according to claim 2, wherein:

the host interface includes at least one state machine and at least one temporary storage device, and

the terminal interface includes at least one other state machine and at least one other temporary storage device.

9. An interface according to claim 8, wherein:

the host interface includes;

a host master state machine and a host incoming temporary storage device together providing a unidirectional path from a first communication medium to the first bridge, and

a host target state machine and a host outgoing temporary storage device together providing a unidirectional path from the first bridge to the first communication medium; and

the terminal interface includes;

a terminal master state machine and a terminal incoming temporary storage device together providing a unidirectional path from a second communication medium to the second bridge, and

a terminal target state machine and a terminal outgoing temporary storage device together providing a unidirectional path from the second bridge to the second communication medium.

10. An interface according to claim 7, wherein the first communications controller comprises a first FPGA and the second communications controller comprises a second FPGA.

11. An interface according to claim 7, wherein the host interface further includes a first ASIC coupled between the first bridge and the first communication medium and the terminal interface further includes a second ASIC coupled between the second bridge and the second communication medium.

12. An interface according to claim 7, wherein the host interface further includes:

a host master state machine coupled to output to the first bridge;

a first FIFO outputting master bus data to the host master state machine;

a host incoming packet processor coupled to the first communication medium to receive packets from the first communication medium, format convert the packets and output the format converted packets to the first FIFO;

a host target state machine coupled to input target bus data from the first bridge;

a second FIFO receiving the target bus data from the host target state machine; and

a host outgoing packet processor coupled to the first communication medium to format the target bus data from the second FIFO into packets and deliver the packets onto the first communication medium; and

wherein the terminal interface further includes;

a terminal master state machine coupled to output to the second bridge;

a third FIFO outputting master bus data to the terminal master state machine;

a terminal incoming packet processor coupled to the second communication medium to receive packets from the second communication medium, format convert the packets and output the format converted packets to the third FIFO;

a terminal target state machine coupled to input target bus data from the second bridge;

a fourth FIFO receiving the target bus data from the terminal target state machine; and

a terminal outgoing packet processor coupled to the second communication medium to format the target bus data from the fourth FIFO into packets and deliver the packets onto the second communication medium.

13. An interface according to claim 9, wherein the host incoming temporary storage device receives data packets from the terminal outgoing temporary storage device.

14. An interface according to claim 9, wherein the host and terminal interfaces provide cut-through switching from the host outgoing storage device to the first communications controller and from the terminal outgoing storage device to the second communications controller, respectively.

15. An interface according to claim 9, wherein the host and terminal interfaces provide store-and-forward switching from the host outgoing storage device to the first communications controller and from the terminal outgoing storage device to the second communications controller, respectively.

16. An interface according to claim 11, wherein the first and second ASICs further respectively include first and second FIFOs.

17. An interface according to claim 11, wherein the first and second ASICs further respectively include first and second pairs of ASICs.

18. An interface according to claim 13, wherein the terminal incoming temporary storage device receives data packets from the host outgoing temporary storage device.

19. An interface according to claim 10, wherein the first and second FPGAs further respectively include first and second pairs of FPGAs.

20. An interface according to claim 18, wherein terminal and host outgoing temporary storage devices retain a certain data packet after sending the certain data packet to, respectively, the host and terminal incoming temporary storage devices and clear said certain data packet only after said respective host and terminal incoming temporary storage devices return acknowledgments corresponding to said certain data packet.

21. An interface according to claim 19, wherein the first and second pairs of FIFOs include buffers to store data already output onto the first communication medium and the second communication medium until receipt of said data is acknowledged.

22. An interface according to claim 19, wherein the first and second pairs of FIFOs include buffers to store data already output onto the first communication medium and the second communication medium and to repeat the stored data output when an acknowledgment is not received after a predetermined time.

23. A computer system, comprising:

a processor;

an applications storage device operatively associated with the processor to provide the processor with applications routines;

local peripheral controllers operatively associated with user computer peripherals and interfacing said applications routines with said user computer peripherals;

a split data bus comprising;

a first data bus onto which the processor and applications storage device communicate;

a second data bus onto which the local peripheral controllers communicate; and

a bus interface coupling the first and second data buses and including at least one clock domain barrier between said first and second data buses;

a first communications controller coupled to the first data bus; and

a second communications controller coupled to the second data bus, wherein communication between the first and second communications controllers is carried by packet-switch-based communications.

24. The computer system according to claim 23, wherein the bus interface further includes a second clock domain barrier.

25. The computer system according to claim 23, wherein the local peripherals include two from the group consisting of:

a video controller;

a sound card;

removable storage; and

a PCI-compliant peripheral controller.

26. The computer system according to claim 23, further including at least one user device comprising at least one of a keyboard and a pointing device, said user device producing user device signals input directly to said bus interface and passing to said first data bus without passing through said second data bus.

27. The computer system according to claim 25, wherein the packet-switch-based communications comprise IP-compatible, packet-switched communications.

28. The computer system according to claim 25, wherein the packet-switch-based communications comprise UDP-compatible, packet-switched communications.

29. The computer system according to claim 25, wherein the packet-switch-based communications comprise ATM-based communications.