Reducing memory overhead of a page table in a dynamic logical partitioning environment

• US 7,783,858 B2
• Filed: 01/20/2007
• Issued: 08/24/2010
• Est. Priority Date: 01/20/2007
• Status: Expired due to Fees

• Current Assignee: LinkedIn Corporation (Microsoft Corporation)
• Original Assignee: International Business Machines Corporation
• Inventors: Lam, Kiet H., Chiang, Men-Chow
• Primary Examiner(s): Shah; Sanjiv
• Assistant Examiner(s): Yu; Jae U
• Application Number:
  US11/625,296
• Publication Number:
  US 20080177974A1
• Time in Patent Office: 1,312 Days
• Field of Search: 711/207, 711/206, 711/173, 711/170
• US Class Current: 711/207
• CPC Class Codes: G06F 12/1018 involving hashing techniques, e.g. inverted page tables
• CPC Class Codes: G06F 12/1036 for multiple virtual address spaces, e.g. segmentation G06F12/1045 takes precedence
• CPC Class Codes: G06F 2212/152 Virtualized environment, e.g. logically partitioned system

Abstract

Mechanisms for reducing memory overhead of a page table in a dynamic logical partitioning (LPAR) environment are provided. Each LPAR, upon its creation, is allowed to declare any maximum main memory size for the LPAR as long as the aggregate maximum main memory size for all LPARs does not exceed the total amount of available main memory. A single page table is used for all of the LPARs. Thus, the only page table in the computing system is shared by all LPARs and every memory access operation from any LPAR must go through the same page table for address translation. As a result, since only one page table is utilized, and the aggregate size of the main memory apportioned to each of the LPARs is limited to the size of the main memory, the size of the page table cannot exceed the size of the main memory.

Claims

1. A method, in a data processing system, for virtualizing access to a main memory, comprising:

allocating portions of the main memory to a plurality of logical partitions in the data processing system;

generating a single shared page table having a plurality of page table entries, wherein the plurality of page table entries comprises page table entries for accessing each of the portions of the main memory allocated to each of the logical partitions in the plurality of logical partitions; and

utilizing the single shared page table to access the portions of the main memory, wherein utilizing the single shared page table to access the portions of the main memory, comprises;

receiving a request from a logical partition, the request specifying a virtual address for an operation to be performed;

appending, via a hardware mechanism, a logical partition identifier to the virtual address, the logical partition identifier being stored in a hardware register; and

retrieving a virtual-to-real address translation from the single shared page table based on a combination of the virtual address and the logical partition identifier appended to the virtual address.

2. The method of claim 1, further comprising:

allocating a logical partition identifier portion of a virtual address space, used by the single shared page table, for specifying a logical partition identifier of an associated logical partition, wherein each logical partition in the plurality of logical partitions has a different unique logical partition identifier.

3. The method of claim 2, wherein, by virtue of the logical partition identifier portion of the virtual address space, each logical partition of the plurality of logical partition generates virtual addresses in their own non-overlapping segments of the virtual address space.

4. The method of claim 2, further comprising:

controlling access to portions of the single shared page table based on the logical partition identifier in the logical partition identifier portion of virtual addresses used to access the single shared page table such that entries in the single shared page table associated with a first logical partition having a first logical partition identifier are not accessible by a second logical partition having a second logical partition identifier.

5. The method of claim 2, wherein the logical partition identifier for a logical partition is assigned to an operating system associated with the logical partition by an input/output virtualization mechanism.

6. The method of claim 5, wherein the logical partition identifiers for each logical partition in the plurality of logical partitions are maintained by the input/output virtualization mechanism, and wherein one logical partition of the plurality of logical partitions cannot access a logical partition identifier of another logical partition in the plurality of logical partitions.

7. The method of claim 1, further comprising:

dynamically modifying an amount of the main memory allocated to a logical partition in the plurality of logical partitions by notifying an input/output virtualization mechanism of the modification, wherein the input/output virtualization mechanism modifies a main memory limit associated with the logical partition and updates main memory pool data structures in response to receiving the notification of the modification.

8. The method of claim 1, wherein each portion of main memory allocated to each logical partition of the plurality of logical partition may be any size portion of the main memory as long as the aggregate of the allocated main memory portions for the plurality of logical partitions does not exceed a total size of the main memory.

9. The method of claim 1, wherein the logical partition identifier stored in the hardware register is only modifiable by a virtualization mechanism upon a logical partition context switch event.

10. A computer program product comprising a computer useable medium having a computer readable program, wherein the computer readable program, when executed on a computing device, causes the computing device to:

allocate portions of the main memory to a plurality of logical partitions in the data processing system;

generate a single shared page table having a plurality of page table entries, wherein the plurality of page table entries comprises page table entries for accessing each of the portions of the main memory allocated to each of the logical partitions in the plurality of logical partitions; and

utilize the single shared page table to access the portions of the main memory, wherein the computer readable program causes the computing device to utilize the single shared page table to access the portions of the main memory by;

receiving a request from a logical partition, the request specifying a virtual address for an operation to be performed;

appending, via a hardware mechanism, a logical partition identifier to the virtual address, the logical partition identifier being stored in a hardware register; and

retrieving a virtual-to-real address translation from the single shared page table based on a combination of the virtual address and the logical partition identifier appended to the virtual address.

11. The computer program product of claim 10, wherein the computer readable program further causes the computing device to:

allocate a logical partition identifier portion of a virtual address space, used by the single shared page table, for specifying a logical partition identifier of an associated logical partition, wherein each logical partition in the plurality of logical partitions has a different unique logical partition identifier.

12. The computer program product of claim 11, wherein, by virtue of the logical partition identifier portion of the virtual address space, each logical partition of the plurality of logical partition generates virtual addresses in their own non-overlapping segments of the virtual address space.

13. The computer program product of claim 11, wherein the computer readable program further causes the computing device to:

control access to portions of the single shared page table based on the logical partition identifier in the logical partition identifier portion of virtual addresses used to access the single shared page table such that entries in the single shared page table associated with a first logical partition having a first logical partition identifier are not accessible by a second logical partition having a second logical partition identifier.

14. The computer program product of claim 11, wherein the logical partition identifier for a logical partition is assigned to an operating system associated with the logical partition by an input/output virtualization mechanism.

15. The computer program product of claim 14, wherein the logical partition identifiers for each logical partition in the plurality of logical partitions are maintained by the input/output virtualization mechanism, and wherein one logical partition of the plurality of logical partitions cannot access a logical partition identifier of another logical partition in the plurality of logical partitions.

16. The computer program product of claim 10, wherein the computer readable program further causes the computing device to:

dynamically modify an amount of the main memory allocated to a logical partition in the plurality of logical partitions by notifying an input/output virtualization mechanism of the modification, wherein the input/output virtualization mechanism modifies a main memory limit associated with the logical partition and updates main memory pool data structures in response to receiving the notification of the modification.

17. The computer program product of claim 10, wherein each portion of main memory allocated to each logical partition of the plurality of logical partition may be any size portion of the main memory as long as the aggregate of the allocated main memory portions for the plurality of logical partitions does not exceed a total size of the main memory.

18. An apparatus, comprising:

a processor; and

a main memory coupled to the processor, wherein the main memory comprises instructions which, when executed by the processor, cause the processor to;

allocate portions of the main memory to a plurality of logical partitions in the data processing system;

generate a single shared page table having a plurality of page table entries, wherein the plurality of page table entries comprises page table entries for accessing each of the portions of the main memory allocated to each of the logical partitions in the plurality of logical partitions; and

utilize the single shared page table to access the portions of the main memory, wherein the instructions cause the processor to utilize the single shared page table to access the portions of the main memory by;

receiving a request from a logical partition, the request specifying a virtual address for an operation to be performed;

appending, via a hardware mechanism, a logical partition identifier to the virtual address, the logical partition identifier being stored in a hardware register; and

retrieving a virtual-to-real address translation from the single shared page table based on a combination of the virtual address and the logical partition identifier appended to the virtual address.