Branch target address cache
First Claim
1. A processor, comprising:
- at least one execution unit that executes instructions; and
instruction sequencing logic, coupled to the at least one execution unit, that fetches instructions from a memory system for execution by the at least one execution unit, said instruction sequencing logic including a branch logic that outputs predicted branch target addresses for use as instruction fetch addresses, said branch logic including a level one branch target address cache (BTAC) and a level two BTAC each having a respective plurality of entries each associating at least a tag with a predicted branch target address;
wherein said branch logic accesses the level one BTAC and the level two BTAC in parallel with at least a tag portion of a first instruction fetch address to obtain a first predicted branch target address from the level one BTAC and a second predicted branch target address from the level two BTAC;
wherein the instruction sequencing logic fetches instructions from the memory system utilizing the first predicted branch target address as a second instruction fetch address in a first processor clock cycle and fetches instructions from the memory system utilizing the second predicted branch target address as a third instruction fetch address in a second processor clock cycle subsequent to the first processor clock cycle.
1 Assignment
0 Petitions
Accused Products
Abstract
A processor includes an execution unit and instruction sequencing logic that fetches instructions from a memory system for execution. The instruction sequencing logic includes branch logic that outputs predicted branch target addresses for use as instruction fetch addresses. The branch logic includes a level one branch target address cache (BTAC) and a level two BTAC each having a respective plurality of entries each associating at least a tag with a predicted branch target address. The branch logic accesses the level one and level two BTACs in parallel with a tag portion of a first instruction fetch address to obtain a first predicted branch target address from the level one BTAC for use as a second instruction fetch address in a first processor clock cycle and a second predicted branch target address from the level two BTAC for use as a third instruction fetch address in a later second processor clock cycle.
37 Citations
17 Claims
-
1. A processor, comprising:
-
at least one execution unit that executes instructions; and instruction sequencing logic, coupled to the at least one execution unit, that fetches instructions from a memory system for execution by the at least one execution unit, said instruction sequencing logic including a branch logic that outputs predicted branch target addresses for use as instruction fetch addresses, said branch logic including a level one branch target address cache (BTAC) and a level two BTAC each having a respective plurality of entries each associating at least a tag with a predicted branch target address; wherein said branch logic accesses the level one BTAC and the level two BTAC in parallel with at least a tag portion of a first instruction fetch address to obtain a first predicted branch target address from the level one BTAC and a second predicted branch target address from the level two BTAC; wherein the instruction sequencing logic fetches instructions from the memory system utilizing the first predicted branch target address as a second instruction fetch address in a first processor clock cycle and fetches instructions from the memory system utilizing the second predicted branch target address as a third instruction fetch address in a second processor clock cycle subsequent to the first processor clock cycle. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
-
-
10. A method of data processing in a processor including at least one execution unit and an instruction sequencing logic containing branch logic, the branch logic including a level one branch target address cache (BTAC) and a level two BTAC, said method comprising:
-
fetching a first instruction from a memory system for execution by at least one execution unit of the processor utilizing a first instruction fetch address; the branch logic accessing the level one BTAC and the level two BTAC in parallel with at least a tag portion of the first instruction fetch address; in response to said accessing; outputting a first predicted branch target address from the level one BTAC; outputting a second predicted branch target address from the level two BTAC; and fetching a second instruction from the memory system utilizing the first predicted branch target address as a second instruction fetch address in a first processor clock cycle and fetching a third instruction from the memory system utilizing the second predicted branch target address as a third instruction fetch address in a second processor clock cycle subsequent to the first processor clock cycle. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
-
Specification