Method for memory testing
First Claim
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1. A method for memory testing, which is implemented on an embedded system, the method comprising:
- loading a booting program when the embedded system is booted;
activating a RAM of the embedded system by the booting program;
duplicating the booting program itself and writing the duplicated booting program into a first section of the RAM by the booting program;
downloading a testing program from an on-line source and writing the downloaded testing program into a second section of the RAM by the duplicated booting program; and
after the downloaded testing program is executed by the duplicated booting program, the downloaded testing program is enabled to circularly check a third section which is the rest part of the RAM excepting the first and second sections, by steps comprising;
respectively testing a plurality of data lines of the third section in the RAM and determining whether any of the data lines thereof causes errors, and terminating the test and outputting an error message while any of the data lines thereof causes errors;
respectively testing a plurality of address lines of the third section in the RAM and determining whether any of the address lines thereof causes errors, and terminating the test and outputting an error message while any of the address lines thereof causes errors;
respectively processing an increment/decrement test to a plurality of memory addresses of the third section in the RAM and determining respectively whether any of the memory addresses thereof causes errors, and terminating the increment/ decrement test and outputting an error message while any of the memory addresses thereof causes errors;
respectively processing a delay test to a plurality of memory addresses of the third section in the RAM and determining respectively whether any of the memory addresses thereof causes errors, and terminating the delay test and outputting an error message while any of the memory addresses thereof causes errors;
respectively processing a burst test to a plurality of memory addresses of the third section in the RAM and determining respectively whether any of the memory addresses thereof causes errors, and terminating the burst test and outputting an error message while any of the memory addresses thereof causes errors; and
respectively processing a random test to a plurality of memory addresses of the third section in the RAM and determining respectively whether any of the memory addresses thereof causes errors, and terminating the random test and outputting an error message while any of the memory addresses thereof causes errors.
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Abstract
A method for memory testing implemented on an embedded system, the method comprising steps of loading a booting program when the embedded system is booted; activating a RAM of the embedded system by the booting program; duplicating the booting program itself and writing the duplicated booting program into a first section of the RAM by the booting program; downloading a testing program from an on-line source and writing the downloaded testing program into a second section of the RAM by the duplicated booting program; and enabling the downloaded testing program to check a third section the rest part of the RAM excepting the first and second sections, after the downloaded testing program is executed by the duplicated booting program.
20 Citations
3 Claims
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1. A method for memory testing, which is implemented on an embedded system, the method comprising:
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loading a booting program when the embedded system is booted; activating a RAM of the embedded system by the booting program; duplicating the booting program itself and writing the duplicated booting program into a first section of the RAM by the booting program; downloading a testing program from an on-line source and writing the downloaded testing program into a second section of the RAM by the duplicated booting program; and after the downloaded testing program is executed by the duplicated booting program, the downloaded testing program is enabled to circularly check a third section which is the rest part of the RAM excepting the first and second sections, by steps comprising; respectively testing a plurality of data lines of the third section in the RAM and determining whether any of the data lines thereof causes errors, and terminating the test and outputting an error message while any of the data lines thereof causes errors; respectively testing a plurality of address lines of the third section in the RAM and determining whether any of the address lines thereof causes errors, and terminating the test and outputting an error message while any of the address lines thereof causes errors; respectively processing an increment/decrement test to a plurality of memory addresses of the third section in the RAM and determining respectively whether any of the memory addresses thereof causes errors, and terminating the increment/ decrement test and outputting an error message while any of the memory addresses thereof causes errors; respectively processing a delay test to a plurality of memory addresses of the third section in the RAM and determining respectively whether any of the memory addresses thereof causes errors, and terminating the delay test and outputting an error message while any of the memory addresses thereof causes errors; respectively processing a burst test to a plurality of memory addresses of the third section in the RAM and determining respectively whether any of the memory addresses thereof causes errors, and terminating the burst test and outputting an error message while any of the memory addresses thereof causes errors; and respectively processing a random test to a plurality of memory addresses of the third section in the RAM and determining respectively whether any of the memory addresses thereof causes errors, and terminating the random test and outputting an error message while any of the memory addresses thereof causes errors. - View Dependent Claims (2, 3)
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Specification
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Current AssigneeInventec Corporation
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Original AssigneeInventec Corporation
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InventorsChu Chen, Chi-Yuan
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Primary Examiner(s)DUNCAN, MARC M
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Application NumberUS12/007,115Publication NumberTime in Patent Office960 DaysField of Search714/36, 714/42, 714/718, 713/2US Class Current714/36CPC Class CodesG06F 11/2284 by power-on test, e.g. powe...G11C 2029/0401 in embedded memoriesG11C 2029/0407 on power onG11C 29/16 using microprogrammed units...
