Yield based retargeting for semiconductor design flow

• US 7,784,019 B1
• Filed: 11/01/2007
• Issued: 08/24/2010
• Est. Priority Date: 11/01/2006
• Status: Expired due to Fees

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Zach, Franz
• Primary Examiner(s): Chiang; Jack
• Assistant Examiner(s): Dimyan; Magid Y
• Application Number:
  US11/934,047
• Time in Patent Office: 1,027 Days
• Field of Search: 716/2, 716/9, 716/19, 716/21
• US Class Current: 716/53
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

A method for modifying an integrated circuit design layout is presented and can include placing a plurality of target points in the proximity of a polygon representing a portion of the integrated circuit design; modifying the target point placement for some or all of the placed target points; fitting a curve to the target points; and redefining the portion of the integrated circuit as a contour defined by the fitted curve to modify the design layout. In some applications the modified design layout can be used as a target for an optical proximity correction algorithm or for other purposes.

Claims

1. A method for modifying an integrated circuit design layout, comprising:

using a computer system to place a plurality of target points in proximity of a polygon representing a portion of an integrated circuit design;

modifying the target point placement for some or all of the placed target points using a yield function;

fitting a curve to the target points; and

redefining the portion of the integrated circuit as a contour defined by the curve to modify the design layout.

2. The method of claim 1, wherein the modified design layout is used as a target for an optical proximity correction algorithm.

3. The method of claim 1, wherein placing comprises placing the target points on the perimeter of the polygon representing the portion of the integrated circuit design.

4. The method of claim 1, further comprising accepting user input identifying target point placement modification.

5. The method of claim 1, further comprising determining the yield function of the integrated circuit design.

6. The method of claim 5, wherein the yield function is determined using a single design layer or multiple design layers of the circuit design.

7. The method of claim 5, wherein the yield function is based on overlay, printability, planarization, material fill, or electrical properties.

8. The method of claim 5, wherein the yield function is described by an error function as:

$Y<br><br>\left(x\right)=\frac{1}{2}<br><br>\left(1+\mathrm{erf}<br><br>\left(\frac{x-\mathrm{\mu <br><br>}}{2<br><br>\mathrm{\sigma <br><br>}}\right)\right)$

where μ

is the position of a contact edge, x is the position of a metal edge and the positive direction is defined as being from the center of the contact to the edge of the contact.

9. The method of claim 1, wherein modifying target point placement is performed iteratively.

10. The method of claim 1, wherein modified target point placement is determined to improve manufacturability of the circuit design.

11. A circuit design optimization tool comprising computer executable program code on a computer readable medium configured to cause a processor to perform the functions of:

placing a plurality of target points in proximity of a polygon representing a portion of an integrated circuit design;

modifying the target point placement for some or all of the placed target points using a yield function;

fitting a curve to the target points; and

redefining the portion of the integrated circuit as a contour defined by the fitted curve to modify the design layout.

12. The circuit design optimization tool of claim 11, wherein the modified design layout is used as a target for an optical proximity correction algorithm.

13. The circuit design optimization tool of claim 11, wherein placing comprises placing the target points on the perimeter of the polygon representing the portion of the integrated circuit design.

14. The circuit design optimization tool of claim 11, further comprising accepting user input identifying target point placement modification.

15. The circuit design optimization tool of claim 11, further comprising determining a yield function of the integrated circuit design.

16. The circuit design optimization tool of claim 15, wherein the yield function is determined using a single design layer or multiple design layers of the circuit design.

17. The circuit design optimization tool of claim 15, wherein the yield function is based on overlay, printability, planarization, material fill, or electrical properties.

18. The circuit design optimization tool of claim 15, wherein the yield function is described by an error function as:

$Y<br><br>\left(x\right)=\frac{1}{2}<br><br>\left(1+\mathrm{erf}<br><br>\left(\frac{x-\mathrm{\mu <br><br>}}{2<br><br>\mathrm{\sigma <br><br>}}\right)\right)$

where μ

is the position of a contact edge, x is the position of a metal edge and the positive direction is defined as being from the center of the contact to the edge of the contact.

19. The circuit design optimization tool of claim 11, wherein modifying target point placement is performed iteratively.

20. The circuit design optimization tool of claim 11, wherein modified target point placement is determined to improve manufacturability of the circuit design.