Method for fabricating micromachined structures

• US 7,785,481 B2
• Filed: 11/21/2007
• Issued: 08/31/2010
• Est. Priority Date: 10/05/2007
• Status: Expired due to Fees

• Current Assignee: PixArt Imaging Incorporated
• Original Assignee: PixArt Imaging Incorporated
• Inventors: WANG, Chuan Wei
• Primary Examiner(s): CULBERT, ROBERTS P
• Application Number:
  US11/944,247
• Publication Number:
  US 20090090693A1
• Time in Patent Office: 1,014 Days
• Field of Search: 216/2, 216/13, 438/48, 438/50
• US Class Current: 216/2
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2201/0132 Dry etching, i.e. plasma etching, barrel etching, reactive ion etching [RIE], sputter etching or ion milling
• CPC Class Codes: B81C 2203/0714 Forming the micromechanical structure with a CMOS process
• CPC Class Codes: B81C 2203/0742 Interleave, i.e. simultaneously forming the micromechanical structure and the CMOS circuit

Abstract

A method for fabricating micromachined structures is provided. At least one cavity is formed on a substrate and then a dielectric material different from the material of the substrate is filled in the at least one cavity. Next, a circuitry layer including a first etch-resistant layer and a dielectric layer is formed above the at least one cavity filled with the dielectric material. A portion of the circuitry layer exposed by the first etch-resistant layer is then etched. Finally, the dielectric material in the at least one cavity is etched out.

Claims

1. A method for fabricating a micromachined structure, comprising the steps of:

providing a substrate;

forming at least one cavity on the substrate;

filling the at least one cavity with a dielectric material different from the material of the substrate;

forming a circuitry layer above the at least one cavity filled with the dielectric material, wherein the circuitry layer comprises a first etch-resistant layer and a dielectric layer;

etching the circuitry layer so that the portion of the dielectric layer exposed by the first etch-resistant layer is removed; and

removing the dielectric material in the at least one cavity by etching.

2. The method as claimed in claim 1, wherein the etching to the circuitry layer is an isotropic etching and the circuitry layer further comprises a second etch-resistant layer which acts as the lateral etch-resistant mask.

3. The method as claimed in claim 2, wherein the isotropic etching to the circuitry layer is performed by hydrofluoric gas.

4. The method as claimed in claim 1, wherein the dielectric material filled in the at least one cavity is an oxide of the substrate.

5. The method as claimed in claim 1, wherein the dielectric material is filled in the at least one cavity by plasma-enhanced chemical vapor deposition.

6. The method as claimed in claim 1, wherein the dielectric material is filled in the at least one cavity by atmospheric pressure chemical vapor deposition.

7. The method as claimed in claim 1, wherein the dielectric material is filled in the at least one cavity by heating the substrate to oxidize the surface of the at least one cavity.

8. The method as claimed in claim 1, further comprising:

removing the portion of the dielectric material covering the surface of the substrate by chemical mechanical polishing.

9. The method as claimed in claim 1, wherein the step of forming at least one cavity on the substrate comprising:

forming a pattern on the substrate by photolithography; and

etching the substrate by inductively coupled plasma to form at least one cavity on the substrate that has a shape corresponding to the shape of the pattern.

10. The method as claimed in claim 1, wherein the at least one cavity has a primary portion and a plurality of protruding portions extending outwardly from the primary portion.

11. The method as claimed in claim 1, wherein a plurality of cavities is formed on the substrate and the portions of the unetched circuitry layer are positioned above the cavities.

12. The method as claimed in claim 2, wherein the first and second etch-resistant layers are metal layers.