Dense non-volatile memory array and method of fabrication

• US 7,786,512 B2
• Filed: 07/18/2006
• Issued: 08/31/2010
• Est. Priority Date: 07/18/2005
• Status: Active Grant

• Current Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Original Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Inventors: Bloom, Ilan, Irani, Rustom, Eitan, Boaz
• Primary Examiner(s): Soward, Ida M
• Application Number:
  US11/489,747
• Publication Number:
  US 20070051982A1
• Time in Patent Office: 1,505 Days
• Field of Search: 252/202, 252207-208, 252/211, 252758-760, 252/E21.575
• US Class Current: 257/202
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/0338 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 29/7923 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A non-volatile memory array includes a multiplicity of memory cells, each of whose area is less than 4 F² per cell (where F is a minimum feature size), and periphery elements to control the memory cells. The present invention also includes a non-volatile memory array which includes word lines and bit lines generally perpendicular to the word lines, with a word line pitch of less than 2 F. In one embodiment, the word lines are made of polysilicon spacers.

Claims

1. A non-volatile memory array comprising:

word lines; and

bit lines generally perpendicular to said word lines, wherein;

(a) a pitch between two neighboring word lines is less than 2 F, (b) said pitch is a word line width and a word line spacing, and (c) a minimum spacing is electrically limited to the point at which a dielectric between neighboring word lines breaks down.

2. The array of claim 1 and wherein said word line pitch is between 1 F and 2 F.

3. The array according to claim 1 and wherein said array is a NROM (nitride read only memory) array.

4. The array according to claim 1 and wherein a distance from a first word line to a word line two away from said first word line is 2 F.

5. The array according to claim 1 and wherein said word line width is at least 0.5 F and said spacing is less than 0.5 F.

6. The array according to claim 1 and wherein said dielectric is oxide-nitride-oxide.

7. The array according to claim 1 and wherein said word lines are formed from polysilicon spacers.

8. The array according to claim 7 and wherein said word lines are at least 0.1 F wide.

10. The chip according to claim 5 and wherein said cells are NROM cells.

9. A non-volatile memory chip comprising:

(a) an array of memory cells each of whose area is less than 4 F² per cell, wherein F is a minimum feature size;

(b) wherein said array also comprises word lines and bit lines generally perpendicular to said word lines such that a pitch between two neighboring word lines is less than 2 F, said pitch is a word line width and a word line spacing, and a minimum spacing is electrically limited to the point at which a dielectric between neighboring word lines breaks down; and

(c) periphery elements to control said memory cells.

11. The chip according to claim 9 wherein gates of rows of said memory cells are formed together into word lines and wherein a word line width is at least 0.5 F and a word line spacing is less than 0.5 F.

12. The chip according to claim 11 and wherein said rows are formed of metal.

13. The chip according to claim 9 wherein gates of rows of said memory cells are formed together into word lines and wherein said word lines are formed from polysilicon spacers.

14. The chip according to claim 13 and wherein said word lines are at least 0.1 F wide.

15. The chip according to claim 13 and wherein a distance from a first word line to a word line two away from said first word line is 2 F.

16. A non-volatile memory array comprising:

polysilicon spacer word lines; and

bit lines generally perpendicular to said word lines, wherein;

(a) a pitch between two neighboring word lines is less than 2 F, (b) said pitch is a word line width and a word line spacing, and (c) a minimum spacing is electrically limited to the point at which a dielectric between neighboring word lines breaks down.

17. The array according to claim 16 and wherein said spacer word lines are at least 0.1 F wide.

18. The array according to claim 16 and wherein a distance from a first word line to a word line two away from said first word line is 2 F.

19. The array according to claim 16 and wherein the width of said word lines is less than 1 F.

20. The array according to claim 19 and wherein said word lines generally pass low currents during programming.