Nonvolatile semiconductor memory device

• US 7,786,526 B2
• Filed: 03/29/2007
• Issued: 08/31/2010
• Est. Priority Date: 03/31/2006
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Furuno, Makoto, Takano, Tamae, Yamazaki, Shunpei, Asami, Yoshinobu
• Primary Examiner(s): Mandala; Victor A
• Application Number:
  US11/730,184
• Publication Number:
  US 20070228449A1
• Time in Patent Office: 1,251 Days
• Field of Search: 257/311, 257/316, 257/324, 257/E29.309
• US Class Current: 257/324
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/44 with a control gate layer also being used as part of the peripheral transistor
• CPC Class Codes: H10B 41/46 with an inter-gate dielectric layer also being used as part of the peripheral transistor
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

It is an object of the present invention to provide a nonvolatile semiconductor memory device which has superior writing characteristics and electric charge retention characteristics. In addition, it is an object of the present invention to provide a nonvolatile semiconductor memory device in which a writing voltage can be reduced. The nonvolatile semiconductor memory device includes a semiconductor region with a channel formation region formed between a pair of impurity regions which are formed to be apart from each other; and a first insulating layer, a charge accumulation layer, a second insulating layer, and a control gate are formed in a location which is a top layer portion of the semiconductor region and which roughly overlaps with the channel formation region. The charge accumulation layer is insulative and is formed as a layer in which electric charge can be trapped.

Claims

1. A nonvolatile semiconductor memory device comprising:

a semiconductor layer including a channel formation region formed between a pair of impurity regions which are apart from each other;

a first insulating layer over the channel formation region;

a charge accumulation layer over the channel formation region with the first insulating layer interposed therebetween;

a second insulating layer over the charge accumulation layer; and

a control gate over the charge accumulation layer with the second insulating layer interposed therebetween,

wherein the charge accumulation layer comprises a compound of germanium with an additional element of nitrogen and the compound is insulative, and

wherein the semiconductor layer is formed on an insulating surface and into an island shape.

2. The nonvolatile semiconductor memory device according to claim 1, wherein the compound is at least one selected from germanium nitride, germanium nitride to which oxygen is added, germanium oxide to which nitrogen is added, germanium nitride to which oxygen and hydrogen are added, and germanium oxide to which nitrogen and hydrogen are added.

3. The nonvolatile semiconductor memory device according to claim 1, wherein the charge accumulation layer is formed at a thickness greater than or equal to 1 nm and less than or equal to 20 nm.

4. The nonvolatile semiconductor memory device according to claim 1, wherein the first insulating layer is a silicon oxide layer, and the silicon oxide layer or an interface of the silicon oxide layer comprises nitrogen.

5. The nonvolatile semiconductor memory device according to claim 4, wherein the silicon oxide layer is formed by a plasma treatment to the semiconductor layer under an oxidizing atmosphere and then treated by nitrogen plasma.

6. The nonvolatile semiconductor memory device according to claim 1, wherein a plurality of charge accumulation layers and control gates are arranged over the semiconductor layer.

7. A nonvolatile semiconductor memory device comprising:

a semiconductor layer including a channel formation region formed between a pair of impurity regions which are apart from each other;

a first insulating layer over the channel formation region;

a charge accumulation layer over the channel formation region with the first insulating layer interposed therebetween;

a second insulating layer over the charge accumulation layer; and

a control gate over the charge accumulation layer with the second insulating layer interposed therebetween, wherein the charge accumulation layer comprises a compound of germanium with an additional element of nitrogen, the compound is insulative and the charge accumulation layer includes particles.

8. The nonvolatile semiconductor memory device according to claim 7, wherein the particles are germanium or silicon-germanium particles.

9. The nonvolatile semiconductor memory device according to claim 7, wherein the compound is at least one selected from germanium nitride, germanium nitride to which oxygen is added, germanium oxide to which nitrogen is added, germanium nitride to which oxygen and hydrogen are added, and germanium oxide to which nitrogen and hydrogen are added.

10. The nonvolatile semiconductor memory device according to claim 7, wherein the charge accumulation layer is formed at a thickness greater than or equal to 1 nm and less than or equal to 20 nm.

11. The nonvolatile semiconductor memory device according to claim 7, wherein the first insulating layer is a silicon oxide layer, and the silicon oxide layer or an interface of the silicon oxide layer comprises nitrogen.

12. The nonvolatile semiconductor memory device according to claim 11, wherein the silicon oxide layer is formed by a plasma treatment to the semiconductor layer under an oxidizing atmosphere and then treated by nitrogen plasma.

13. The nonvolatile semiconductor memory device according to claim 7, wherein a plurality of charge accumulation layers and control gates are arranged over the semiconductor layer.

14. The nonvolatile semiconductor memory device according to claim 7, wherein the semiconductor layer is formed on an insulating surface.

15. The nonvolatile semiconductor memory device according to claim 7, wherein the semiconductor layer is a semiconductor substrate.