Design structures for high-voltage integrated circuits

• US 7,786,535 B2
• Filed: 03/31/2008
• Issued: 08/31/2010
• Est. Priority Date: 01/11/2008
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Lee, Tom C., Mitra, Souvick, Putnam, Christopher S., Li, Junjun, Gauthier, Robert J. Jr., Abou-Khalil, Michel J.
• Primary Examiner(s): Wilson; Allan R.
• Application Number:
  US12/059,034
• Publication Number:
  US 20090179268A1
• Time in Patent Office: 883 Days
• Field of Search: 257/348, 257/365, 257/E27.112, 257/E29.04
• US Class Current: 257/365
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

Design structures for high-voltage integrated circuits. The design structure, which is formed using a semiconductor-on-insulator (SOI) substrate, may include device structure with a semiconductor body positioned between first and second gate electrodes. The first and second gate electrodes and the semiconductor body may be formed from the monocrystalline SOI layer of the SOI substrate. A dielectric layer separates each of the first and second gate electrodes from the semiconductor body. These dielectric layers are formed by defining trenches in the SOI layer and filling the trenches with a dielectric material, which may occur concurrently with a process forming other device isolation regions.

Claims

1. A design structure embodied in a non-transient machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

a first gate electrode;

a second gate electrode,

a semiconductor body including a source, a drain, and a channel between the source and the drain, the semiconductor body positioned laterally on the insulating layer between the first gate electrode and the second gate electrode;

a first gate dielectric layer disposed between the semiconductor body and the first gate electrode; and

a second gate dielectric layer disposed between the semiconductor body and the second gate electrode, the second gate dielectric layer in contact with the semiconductor body;

wherein the semiconductor body, the first gate electrode, the second gate electrode, the first gate dielectric layer, and the second gate dielectric layer each have a contacting relationship with the insulating layer.

2. The design structure of claim 1 wherein the design structure comprises a netlist.

3. The design structure of claim 1 wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.

4. The design structure of claim 1 wherein the design structure resides in a programmable gate array.

5. The design structure of claim 1 wherein the semiconductor body contains a monocrystalline semiconductor material composed primarily of silicon, the channel of the semiconductor body is doped with a first impurity having an first conductivity type, and the source and the drain of the semiconductor body are doped with a second impurity having an second conductivity type opposite to the first conductivity type.

6. The design structure of claim 5 wherein the first gate electrode and the second gate electrode each contain the monocrystalline semiconductor material doped with a concentration of the first impurity or a concentration of the second impurity.

7. The design structure of claim 1 wherein the semiconductor body, the first gate electrode, and the second gate electrode each contain a monocrystalline semiconductor material composed primarily of silicon, the channel, the source, and the drain of the semiconductor body are doped with a first impurity having an first conductivity type, and the first gate electrode and the second gate electrode of the semiconductor body are doped with a second impurity having an second conductivity type opposite to the first conductivity type.

8. The design structure of claim 7 further comprising:

a first portion of the monocrystalline semiconductor material extending through the first gate dielectric layer to connect the semiconductor body and the first gate electrode; and

a second portion of the monocrystalline semiconductor material extending through the second gate dielectric layer to connect the semiconductor body and the second gate electrode.

9. The design structure of claim 7 further comprising:

a first transition zone in the monocrystalline semiconductor material of the semiconductor body across which a net conductivity changes from the first conductivity type of the semiconductor body to the second conductivity type of the first gate electrode; and

a second transition zone in the monocrystalline semiconductor material of the semiconductor body across which the net conductivity changes from the first conductivity type of the semiconductor body to the second conductivity type of the second gate electrode.

10. The design structure of claim 1 wherein the first gate electrode, the second gate electrode, and the semiconductor body contain a monocrystalline semiconductor material composed primarily of silicon, and the first gate dielectric layer and the second gate dielectric layer are composed of silicon dioxide.

11. The design structure of claim 1 further comprising:

a third gate dielectric layer disposed between the first gate electrode and another semiconductor body adjacent to the first gate electrode, the third gate dielectric layer having the contacting relationship with the insulating layer.

12. The design structure of claim 1 further comprising:

a third gate electrode positioned relative to the semiconductor body such that the channel of the semiconductor body is between the third gate electrode and the insulating layer; and

a third gate dielectric layer disposed between the third gate electrode and the second gate electrode.

13. The design structure of claim 1 wherein the semiconductor body, the first gate electrode, and the second gate electrode are adjacent portions of a semiconductor layer carried on the insulating layer, the first gate dielectric layer is formed in a first trench extending from a top surface of the semiconductor layer to the insulating layer, and the second gate dielectric layer is formed in a second trench extending from the top surface of the semiconductor layer to the insulating layer.

14. The design structure of claim 1 wherein the first gate dielectric layer and the second gate dielectric layer have different widths.