System in package (SIP) structure

• US 7,786,572 B2
• Filed: 09/13/2005
• Issued: 08/31/2010
• Est. Priority Date: 09/13/2005
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Hsien-Wei
• Primary Examiner(s): Chambliss; Alonzo
• Application Number:
  US11/225,648
• Publication Number:
  US 20070057357A1
• Time in Patent Office: 1,813 Days
• Field of Search: None
• US Class Current: 257/724
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48147 with an intermediate bond, e.g. continuous wire daisy chain
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2224/73207 Bump and wire connectors
• CPC Class Codes: H01L 2224/73257 Bump and wire connectors
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06527 : Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06593 : Mounting aids permanently on device; arrangements for alignment use of temporary supports H01L21/6835
• CPC Class Codes: H01L 23/544 : Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias

Abstract

A System In Package (SIP) arrangement and method of connecting a plurality of flip chips and wire bond chips with reduced wiring complexity and increase flexibility. The SIP arrangement includes at least one wire bond chip and at least one flip chip.

Claims

1. An electronic package that includes a multiplicity of stacked electronic flip chip circuits, said package comprising:

a connection surface or substrate defining first electrical traces and second electrical traces thereon, said first electrical traces extending from first wire bond pads to first contact pads, said second electrical traces extending from second wire bond pads to fourth contact pads;

a first flip chip having an active side and a back side, said active side comprising first electrical circuits connected to a first multiplicity of bump contacts on said active side, said multiplicity of bump contacts in electrical contact with said first contact pads and fourth contact pads on said connection surface, said back side of the first flip chip defining electrical traces extending from second contact pads and electrically connected to third wire bond pads;

a second flip chip having an active side and a back side and having second electrical circuits connected to a second multiplicity of bump contacts on said active side, said second multiplicity of bump contacts positioned to be in electrical contact with said second contact pads on said first flip chip, said back side of the second flip chip comprising third contact pads and fourth wire bond pads, said second flip chip comprising a via connecting an active circuit on said active side of the second flip chip to either the third contact pads or the fourth wire bond pads;

a third flip chip including a third multiplicity of bump contacts in electrical contact with said third contact pads;

at least one wire bond connected between one of said third wire bond pads on said back side of said first flip chip and one of said second wire bond pads on said connection surface; and

at least one second wire bond connected directly between one of said fourth wire bond pads on said back side of said second flip chip and one of said first wire bond pads on said connection surface.

2. The electronic package of claim 1 wherein said third contact pads are on said backside of said second flip chip such that said third flip chip is stacked on top of said second flip chip, and wherein said third contact pads are connected by electrical traces to said fourth wire bond pads.

3. The electronic package of claim 2 further comprising an electrical connection between one of said second electrical circuits and one of said third contact pads on said back side of said second flip chip.

4. The electronic package of claim 1 further comprising at least one wire bond connected between said back side of said second flip chip and said second wire bond pads on said connection surface.

5. An electronic package that includes a multiplicity of stacked electronic flip chip circuits, said package comprising:

a connection surface or substrate defining electrical traces thereon, said electrical traces extending from first wire bond pads to first contact pads, and further comprising second wire bond pads;

a first flip chip having an active side and a back side, said active side comprising first electrical circuits connected to a first multiplicity of bump contacts on said active side, said multiplicity of bump contacts in electrical contact with said first contact pads on said connection surface, said back side of the first flip chip defining electrical traces extending from second contact pads and electrically connected to third wire bond pads;

a second flip chip having an active side and a back side and having second electrical circuits connected to a second multiplicity of bump contacts on said active side, said second multiplicity of bump contacts positioned to be in electrical contact with said second contact pads on said first flip chip and fourth wire bond pads located on the back side of the second flip chip;

a third flip chip including a third multiplicity of bump contacts in electrical contact with third contact pads, said third contact pads on said connection surface;

at least one wire bond connected between one of said third wire bond pads on said back side of said first flip chip and one of said second wire bond pads on said connection surface; and

at least one wire bond connected between said third wire bond pads on said first flip chip and fourth wire bond pads;

wherein said back side of said third flip chip further includes fourth contact pads and wherein said second flip chip further includes a fourth multiplicity of bump contact positioned to be in contact with said fourth contact pads on said third flip chip such that said second flip chip bridges and connects to both said first and third flip chips.

6. An electronic package having a stacked plurality of electronic circuit chips comprising:

a connection surface defining contact pads for electrically connecting at least one of said plurality of electronic circuit chips;

at least one flip chip in said stacked plurality of electronic circuit chips;

a back side surface on said flip chip having wire bond pads;

at least one wire bond connected between one of said wire bond pads on said back side surface on said flip chip and a second wire bond pad on a back side surface of a second chip of said stacked plurality of electronic circuit chips;

a third chip located between the second chip and the connection surface, the third chip being connected to the contact pads through first bump contacts on a first side and also connected to the second chip through second bump contacts on a second side; and

at least one wire bond connected directly between one of said wire bond pads on said back side surface of said second chip and a third wire bond pad on said connection surface, wherein the third wire bond pad is connected to at least one of the contact pads.