Chip capacitive coupling

• US 7,786,592 B2
• Filed: 01/10/2006
• Issued: 08/31/2010
• Est. Priority Date: 06/14/2005
• Status: Active Grant

• Current Assignee: Cufer Asset Ltd LLC (Intellectual Ventures LLC)
• Original Assignee: Cufer Asset Ltd LLC (Intellectual Ventures LLC)
• Inventors: Trezza, John
• Primary Examiner(s): Le; Thao X
• Assistant Examiner(s): TRICE, KIMBERLY N
• Application Number:
  US11/329,952
• Publication Number:
  US 20060278986A1
• Time in Patent Office: 1,694 Days
• Field of Search: 257/686, 257/744
• US Class Current: 257/777
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05023 the whole internal layer protruding from the surface
• CPC Class Codes: H01L 2224/05026 the internal layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/0508 being stacked
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05664 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/0615 Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/1358 being stacked
• CPC Class Codes: H01L 2224/13609 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/16 : of an individual bump connector
• CPC Class Codes: H01L 2224/24226 : the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/75305 : comprising protrusions
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06524 : Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06531 : Non-galvanic coupling, e.g. capacitive coupling
• CPC Class Codes: H01L 2225/06534 : Optical coupling
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06555 : Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01025 : Manganese [Mn]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01051 : Antimony [Sb]
• CPC Class Codes: H01L 2924/01061 : Promethium [Pm]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A method of creating a semiconductor chip having a substrate, a doped semiconductor material abutting the substrate and a device pad at an outer side of the doped semiconductor material involves creating a via through at least a portion of the substrate, the via having a periphery and a bottom at a location and depth sufficient to bring the via into proximity with the device pad but be physically spaced apart from the device pad, introducing an electrically conductive material into the via, and connecting the electrically conductive material to a signal source so the signal will deliberately be propagated from the electrically conductive material to the device pad without any direct electrical connection existing between the electrically conductive material and the device pad.

Claims

1. A method of creating a semiconductor chip, wherein the semiconductor chip comprises a substrate, a doped semiconductor material abutting the substrate, and a device pad at an outer surface of the doped semiconductor material, the method comprising:

creating a via through at least a portion of the substrate, wherein the via extends from an outer surface of the substrate into the substrate, wherein the via has a periphery, wherein at least a portion of the periphery is bounded by the substrate, and wherein the via has a bottom and a depth sufficient to bring the via into proximity with, but physically spaced apart from, the device pad;

introducing an electrically conductive material into the via; and

connecting the electrically conductive material to a signal source in a configuration such that when a signal is applied by the signal source to the electrically conductive material, the signal will be propagated from the electrically conductive material to the device pad without any direct electrical connection between the electrically conductive material and the device pad.

2. The method of claim 1, further comprising introducing an electrically insulating material into the via prior to said introducing the electrically conductive material into the via, wherein the electrically insulating material is configured to isolate the electrically conductive material from the substrate.

3. The method of claim 1, wherein said creating the via further comprises extending the via into at least a portion of the doped semiconductor material so that at least another portion of the periphery is bounded by the doped semiconductor material.

4. The method of claim 3, wherein, prior to said introducing the electrically conductive material into the via, the method further comprises introducing an electrically insulating material into the via about the periphery, thereby electrically isolating the electrically conductive material from at least the doped semiconductor material.

5. The method of claim 1, wherein said introducing the electrically conductive material into the via comprises forming a coaxial conductor within the via, wherein the coaxial conductor comprises a first electrical conductor bounded about its periphery by a first insulator, and wherein the first insulator is bounded about its periphery by a second electrical conductor.

6. The method of claim 5, wherein, prior to said introducing the electrically conductive material into the via, the method further comprises introducing an electrically insulating material into the via about the periphery of the via, thereby electrically isolating the second electrical conductor from at least the doped semiconductor material.

7. The method of claim 1, wherein said introducing the electrically conductive material into the via comprises forming a triaxial conductor within the via, wherein the triaxial conductor comprises a first electrical conductor bounded about its periphery by a first insulator, wherein the first insulator is bounded about its periphery by a second electrical conductor, wherein the second electrical conductor is bounded about its periphery by a second insulator, and wherein the second insulator is bounded about its periphery by a third electrical conductor.

8. The method of claim 7, wherein, prior to said introducing the electrically conductive material into the via, the method further comprises introducing an electrically insulating material into the via about the periphery of the via, thereby electrically isolating the third electrical conductor from at least the doped semiconductor material.

9. The method of claim 1, further comprising stacking the semiconductor chip onto a second semiconductor chip so that the electrically conductive material is proximate to a device pad of the second semiconductor chip, thereby forming a path for the signal to be propagated between the electrically conductive material and the device pad of the second semiconductor chip.

10. The method of claim 9, further comprising joining a third semiconductor chip onto the semiconductor chip, wherein the third semiconductor chip has a signal conductor, and wherein the signal conductor is coupled to the device pad of the semiconductor chip.

11. The method of claim 1, wherein the semiconductor chip comprises a first semiconductor chip, wherein the method further comprises forming a second semiconductor chip according to the method of claim 1 and stacking the first and second semiconductor chips so that the electrically conductive material of one of the first or second semiconductor chips abuts the device pad of the other of the first or second semiconductor chips, and wherein the first and second semiconductor chips, when stacked, form a unit.

12. The method of claim 11, further comprising:

forming a third semiconductor chip according to the method of claim 1; and

stacking the third semiconductor chip onto the unit so that the electrical conductor of the third semiconductor chip is proximate to an exposed device pad of the unit.

13. The method of claim 11, further comprising:

forming a third semiconductor chip according to the method of claim 1; and

stacking the third semiconductor chip onto the unit so that the device pad of the third semiconductor chip abuts an exposed electrically conductive material of the unit.

27. The method of claim 1, wherein the configuration allows the signal to propagate from the electrically conductive material to the device pad via capacitive coupling.

14. A method for creating a semiconductor chip comprising a substrate, a doped semiconductor material abutting the substrate, and a device pad at an outer side of the doped semiconductor material, the method comprising:

forming a via through at least a portion of the substrate, the via being proximate the device pad and extending from an outer side of the substrate into the substrate, wherein the via has a periphery that is at least partially bounded by the substrate;

providing an electrically conductive material in the via; and

coupling the electrically conductive material to a signal source in a configuration such that a signal applied by the signal source to the electrically conductive material will propagate from the electrically conductive material to the device pad without a direct electrical connection between the electrically conductive material and the device pad.

15. The method of claim 14, further comprising providing an electrically insulating material in the via before said providing an electrically conductive material in the via, wherein the electrically insulating material isolates the electrically conductive material from the substrate.

16. The method of claim 14, wherein said forming a via further comprises extending the via into at least a portion of the doped semiconductor material so that at least another portion of the periphery is bounded by the doped semiconductor material.

17. The method of claim 16, further comprising providing an electrically insulating material in the via about the periphery of the via before said providing an electrically conductive material in the via, wherein the electrically insulating material electrically isolates the electrically conductive material from at least the doped semiconductor material.

18. The method of claim 14, wherein said providing an electrically conductive material in the via comprises forming a coaxial conductor within the via, wherein the coaxial conductor comprises a first electrical conductor bounded about its periphery by a first insulator, and wherein the first insulator is bounded about its periphery by a second electrical conductor.

19. The method of claim 18, further comprising providing an electrically insulating material in the via before said providing an electrically conductive material in the via, wherein the electrically isolating material electrically isolates the second electrical conductor from at least the doped semiconductor material.

20. The method of claim 14, wherein said providing an electrically conductive material in the via comprises providing a triaxial conductor within the via, wherein the triaxial conductor comprises a first electrical conductor bounded about its periphery by a first insulator, and wherein the first insulator is bounded about its periphery by a second electrical conductor, the second electrical conductor is bounded about its periphery by a second insulator, and the second insulator is bounded about its periphery by a third electrical conductor.

21. The method of claim 20, further comprising providing an electrically insulating material in the via to electrically isolate the third electrical conductor from at least the doped semiconductor material.

22. The method of claim 14, further comprising stacking the semiconductor chip onto a second semiconductor chip so that the electrically conductive material is proximate a device pad of the second semiconductor chip and is configured to form a path for the signal to be propagated between the electrical conductive material and the device pad of the second semiconductor chip.

23. The method of claim 22, further comprising joining a third semiconductor chip onto the semiconductor chip, wherein the third semiconductor chip has a signal conductor, and wherein the signal conductor is coupled to the device pad of the semiconductor chip.

24. The method of claim 14, further comprising stacking the semiconductor chip and a second semiconductor chip to form a unit, wherein electrically conductive material of one of the two semiconductor chips abuts a device pad of the other of the two semiconductor chips.

25. The method of claim 24, further comprising stacking a third semiconductor chip onto the unit so that electrically conductive material of the third semiconductor chip is proximate to an exposed device pad of the unit.

26. The method of claim 24, further comprising stacking a third semiconductor chip onto the unit so that a device pad of the third semiconductor chip abuts an exposed electrically conductive material of the unit.