Method of low power PLL for low jitter demanding applications

• US 7,786,809 B1
• Filed: 03/04/2008
• Issued: 08/31/2010
• Est. Priority Date: 03/04/2008
• Status: Active Grant

• Current Assignee: VLSI Technology LLC (SoftBank Group Corp.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Wadhwa, Sanjay, Priel, Michael, Koch, Lavi
• Primary Examiner(s): KINKEAD, ARNOLD M
• Application Number:
  US12/041,687
• Time in Patent Office: 910 Days
• Field of Search: 331/1.A, 331/16, 331/34, 331/177.R, 331/175, 327/156
• US Class Current: 331/16
• CPC Class Codes: H03L 2207/08 Modifications of the phase-locked loop for ensuring constant frequency when the power supply fails or is interrupted, e.g. for saving power
• CPC Class Codes: H03L 7/08 Details of the phase-locked loop
• CPC Class Codes: H03L 7/146 by using digital means for generating the oscillator control signal H03L7/141, H03L7/143 take precedence

Abstract

A system that includes a phase locked loop and an activation circuit; wherein the phase locked loop includes an oscillator, a frequency divider, a phase detector, a control circuit, and a memory circuit. The activation circuit is adapted to activate the memory circuit and the oscillator; to deactivate the frequency divider, the phase detector and the control circuit during deactivation periods and to activate the frequency divider, the phase detector and the control circuit during activation periods. The timing relationship between a deactivation period and an activation period is responsive to an output signal jitter limitation and to a power consumption limitation.

Claims

1. A system comprising a phase locked loop and an activation circuit;

wherein the phase locked loop comprises;

an oscillator adapted to output an output signal having an output frequency in response to a control signal;

a frequency divider, coupled to the oscillator, adapted to generate a feedback signal that has a feedback frequency that is a fraction of the output frequency;

a phase detector, coupled to the frequency divider and to a reference signal source, adapted to output a phase error signal that represents a phase difference between the feedback signal and the reference signal;

a control circuit, adapted to receive the phase error signal and to generate the control signal;

a memory circuit, adapted to store the control signal; and

an activation circuit, adapted to activate the memory circuit and the oscillator; and

to deactivate the frequency divider, the phase detector and the control circuit during deactivation periods and to activate the frequency divider, the phase detector and the control circuit during activation periods;

wherein a timing relationship between a deactivation period and an activation period is responsive to an output signal jitter limitation and to a power consumption limitation.

2. The system according to claim 1 comprising a timing control circuit that is adapted to determine the timing relationship.

3. The system according to claim 2 wherein the timing control circuit is adapted to determine a duration of a deactivation period in response to relationship between a maximal allowable output signal jitter level and output signal jitter level expected to be developed during the deactivation period.

4. The system according to claim 2 wherein the timing control circuit is adapted to receive an output signal jitter indication and evaluate the timing relationship in response to the output signal jitter indication.

5. The system according to claim 1 comprising a timing control circuit that is adapted to receive timing relationship information and in response to the timing relationship information deactivate the frequency divider, the phase detector and the control circuit during the deactivation period and activate the frequency divider, the phase detector and the control circuit during the activation period.

6. The system according to claim 2 wherein the timing control circuit is adapted to determine the relationship between a deactivation period and an activation period in response to a jitter level associated with an application that is executed by utilizing the output signal.

7. The system according to claim 1 wherein the activation circuit is adapted to deactivate the frequency divider, the phase detector and the control circuit during deactivation periods of equal duration and wherein the activation circuit is adapted to activate the frequency divider, the phase detector and the control circuit during activation periods of equal duration.

8. The system according to claim 1 wherein the oscillator is selected from a list consisting of a voltage controlled oscillator, a current controlled oscillator, an LC tank oscillator and a digitally controlled oscillator and wherein the activation circuit activates the memory circuit and the oscillator by providing a high frequency clock signal and a supply voltage.

9. The system according to claim 1 wherein the phase locked loop generates an output signal that is utilized by a digital circuit that is coupled to a mixed signal circuit.

10. The system according to claim 1 comprising a codec that is coupled to a digital circuit that receives the output signal.

11. A method for power consumption reduction, the method comprises:

storing at a memory circuit a control signal obtained during an activation period of a frequency divider, a phase detector and a control circuit of a phase locked loop;

deactivating the frequency divider, the phase detector and the control circuit of the phase locked loop while activating the control circuit and the oscillator during a deactivation period that follows the activation period so as to generate an output signal that is responsive to a control signal stored at the memory circuit;

wherein a timing relationship between the deactivation period and the activation period is responsive to an output signal jitter limitation and to a power consumption limitation.

12. The method according to claim 11 comprising determining the timing relationship.

13. The method according to claim 12 comprising determining a duration of the deactivation period in response to a relationship between a maximal allowable output signal jitter level and output signal jitter level expected to be developed during the deactivation period.

14. The method according to claim 12 comprising receiving an output signal jitter indication and evaluating the timing relationship in response to the output signal jitter indication.

15. The method according to claim 12 comprising receiving timing relationship information.

16. The method according to claim 12 comprising receiving a application information indicative of an application that is executed by utilizing the output signal;

and in response to the application information determining the timing relationship.

17. The method according to claim 12 comprising deactivating the frequency divider, the phase detector and the control circuit during deactivation periods of equal duration and activating the frequency divider, the phase detector and the control circuit during activation periods of equal duration.

18. The method according to claim 12 wherein the deactivation comprising clock gating or power gating.

19. The method according to claim 12 comprising supplying the output signal to a digital circuit that is coupled to a mixed signal circuit.

20. The method according to claim 12 comprising supplying the output signal to a digital circuit that is coupled to a codec.