Interleaved voltage controlled oscillator
First Claim
1. A data processing system comprising a central processing unit (CPU), operable to generate a clock signal, the CPU having an interleaved voltage-controlled oscillator (VCO) comprising:
- a ring circuit comprising a series connection of main logic inverter gates;
a plurality of delay elements connected in parallel with a selected sequence of the main logic inverter gates;
wherein each delay element comprises;
a feedforward section, comprising controls for regulating signal transmission through feedforward elements responsive to one or more control voltages; and
a proportional section, comprising controls for regulating signal transmission through at least one logic inverter gate;
at least one temperature compensation circuit comprising a logic inverter gate in series connection with one or more field effect transistor, the field effect transistors responsive to a compensating voltage input that is proportional to temperature;
an electronic circuit in signal communication with the at least one temperature compensation circuit and configured to provide a voltage signal responsive to temperature;
an amplifier in connection with the electronic circuit to amplify the voltage signal;
a DC offset generator configured to adjust the amplified voltage signal, thereby providing the compensating voltage input;
a random access memory (RAM) configured to store operating commands;
a read only memory (ROM) configured to store BIOS and recovery code; and
an I/O adapter, and a bus system coupling the CPU to the ROM, the I/O adapter, and the RAM.
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Accused Products
Abstract
An interleaved voltage-controlled oscillator (VCO) is disclosed. The VCO includes a ring circuit comprising a series connection of main logic inverter gates, a plurality of delay elements connected in parallel with a selected sequence of the main logic inverter gates, at least one temperature compensation circuit comprising a logic inverter gate in series connection with one or more field effect transistors, the field effect transistor responsive to a compensating voltage input that is proportional to temperature, and an electronic circuit in signal communication with the at least one temperature compensation circuit and configured to provide a voltage signal responsive to temperature. Each delay element includes a feedforward section, comprising controls for regulating signal transmission through feedforward elements responsive to one or more control voltages, and a proportional section, comprising controls for regulating signal transmission through at least one logic inverter gate.
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Citations
7 Claims
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1. A data processing system comprising a central processing unit (CPU), operable to generate a clock signal, the CPU having an interleaved voltage-controlled oscillator (VCO) comprising:
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a ring circuit comprising a series connection of main logic inverter gates; a plurality of delay elements connected in parallel with a selected sequence of the main logic inverter gates; wherein each delay element comprises; a feedforward section, comprising controls for regulating signal transmission through feedforward elements responsive to one or more control voltages; and a proportional section, comprising controls for regulating signal transmission through at least one logic inverter gate; at least one temperature compensation circuit comprising a logic inverter gate in series connection with one or more field effect transistor, the field effect transistors responsive to a compensating voltage input that is proportional to temperature; an electronic circuit in signal communication with the at least one temperature compensation circuit and configured to provide a voltage signal responsive to temperature; an amplifier in connection with the electronic circuit to amplify the voltage signal; a DC offset generator configured to adjust the amplified voltage signal, thereby providing the compensating voltage input; a random access memory (RAM) configured to store operating commands; a read only memory (ROM) configured to store BIOS and recovery code; and an I/O adapter, and a bus system coupling the CPU to the ROM, the I/O adapter, and the RAM. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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Specification