Fabrication of inductors in transformer based tank circuitry

• US 7,786,836 B2
• Filed: 07/19/2005
• Issued: 08/31/2010
• Est. Priority Date: 07/19/2005
• Status: Active Grant

• Current Assignee: Intellectual Ventures Holding 81 LLC (Intellectual Ventures LLC)
• Original Assignee: LC Tank LLC
• Inventors: Gabara, Thaddeus John
• Primary Examiner(s): NGUYEN, TUYEN T
• Application Number:
  US11/184,767
• Publication Number:
  US 20070018767A1
• Time in Patent Office: 1,869 Days
• Field of Search: 336/65, 336/83, 336/200, 336206-208, 336/232, 257/531
• US Class Current: 336/200
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01F 2017/0053 with means to reduce eddy currents
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2924/19015 including thin film passive components
• CPC Class Codes: H01L 2924/19042 being an inductor
• CPC Class Codes: H01L 2924/19104 on the semiconductor or solid-state device, i.e. passive-on-chip

Abstract

Placing inductors or resistors in parallel causes the combined value of inductance or resistance to decrease according to the parallel combination rule. This invention decreases the parasitic resistance of an inductor by placing several inductors in parallel. Furthermore, by careful placement of these inductors, the mutual inductance between these inductors can be used to increase the equivalent inductance value to a value near that of the original inductance value of a single inductor. Thus, it is possible to create an inductance with a much lower value of parasitic resistance. This invention allows the formation of high Q inductors and would be beneficial in any circuit design requiring inductances. Another aspect of this invention is that the coils can be partitioned to minimize eddy current losses. This invention can easily be implemented in a planar technology. Simulations of several tank circuits indicate that the power dissipation can be reduced 3 to 4 times when compared to conventional techniques.

Claims

1. A planar inductor comprising:

a plurality of substrates;

a plurality of dielectric layers;

a first port and a second port;

a coil comprising;

a metallic trace patterned to form the coil; and

each end of the coil is coupled to a first lead and a second lead, respectively;

at least two coils;

the first coil is on a first dielectric layer on a first substrate;

the second coil is on a different dielectric layer on a second substrate;

the first lead of each coil is coupled to the first port; and

the second lead of each coil is coupled to the second port.

2. The inductor of claim 1 further comprising;

at least two coils positioned over one another.

3. The inductor of claim 1 further comprising;

at least one coil having a magnetic coupling to the second coil.

4. The inductor of claim 1 whereby;

the coils can be multi-turn coils.

5. The inductor of claim 1 further comprising:

a plurality of solder bumps;

whereby

the first lead of the second coil is coupled to the first lead of the first coil using at least one solder bump, and

the second lead of the second coil is coupled to the second lead of the first coil using at least one different solder bump.

6. The inductor of claim 1 further comprising:

a plurality of vias;

at least one via couples the first lead of each coil to the first port; and

at least one different via couples the second lead of each coil to the second port.

7. The inductor of claim 1, whereby the first substrate is connected to the second substrate using an MCM (Multi-Chip Module) technology.

8. The inductor of claim 1, wherein the coil comprises:

at least one metal trace;

at least one portion of the metal trace is patterned on a first dielectric layer;

the remaining portions of the metal trace are patterned on the first dielectric layer or at least one different dielectric layer;

all portions are coupled in a series circuit to form the coil; and

each end of the coil is coupled to a first lead and a second output lead, respectively.

9. The inductor of claim 7, wherein the coil comprises:

at least two coils in parallel.

10. A planar inductor comprising:

a first coil formed on a first substrate;

a second coil formed on a second substrate;

wherein

each coil has a first lead and a second lead;

a plurality of solder bumps;

whereby

the first lead of the first coil is coupled to the first lead of the second coil using at least one solder bump, and

the second lead of the first coil is coupled to the second lead of the first coil using at least one different solder bump.

11. The inductor of claim 10, wherein the coil comprises:

a metallic trace patterned to form the coil; and

each end of the coil is coupled to the first lead and the second lead, respectively.

12. The inductor of claim 11, wherein the metallic trace comprises:

at least one metal trace;

at least one portion of the metal trace is patterned on a first dielectric layer;

the remaining portions of the metal trace are patterned on the first dielectric layer or at least one different dielectric layer;

all portions are coupled in a series circuit to form the coil; and

each end of the coil is coupled to a first lead and a second output lead, respectively.

13. The inductor of claim 10, wherein the first coil has a magnetic coupling to the second coil.

14. The inductor of claim 10, whereby the coils can be multi-turn coils.

15. The inductor of claim 10, wherein the two coils are positioned over one another.

16. The inductor of claim 10, wherein the coil in each substrate can be formed of two or more coils connected in parallel.

17. The inductor of claim 16, wherein a plurality of vias;

at least one via couples the first lead of two coils on the same substrate; and

at least one different via couples the second lead of these two coils.

18. The inductor of claim 10, wherein the first substrate is connected to the second substrate using an MCM (Multi-Chip Module) technology.