Real-time configurable masking

• US 7,787,102 B2
• Filed: 11/07/2007
• Issued: 08/31/2010
• Est. Priority Date: 01/13/2004
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Bornstein, William, Spielberg, Anthony Cappa
• Primary Examiner(s): Glick; Edward J
• Assistant Examiner(s): KREUTZER, COLIN WRIGHT
• Application Number:
  US11/936,782
• Publication Number:
  US 20080151208A1
• Time in Patent Office: 1,028 Days
• Field of Search: 250/492.2, 250/492.22, 355/46, 355/53, 355/67, 355/70, 355/77, 359/855, 378 34- 35, 430/5, 430/20, 430/30, 430/311, 430322-324, 430/394
• US Class Current: 355/46
• CPC Class Codes: G03F 7/70291 Addressable masks, e.g. spatial light modulators [SLMs], digital micro-mirror devices [DMDs] or liquid crystal display [LCD] patterning devices
• CPC Class Codes: G03F 7/70466 Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature stitching G03F7/70475

Abstract

Methods, systems, and media to define a portion of a circuit pattern with a source of real-time configurable imaging are disclosed. Embodiments include hardware and/or software for directing a beam through a mask onto a wafer surface to outline a circuit pattern having an undefined area, directing a second beam to the semiconductor wafer surface to define a circuit structure in the undefined area to complete the circuit pattern on the semiconductor wafer surface, and directing the second beam onto a source of real-time configurable imaging. Embodiments may also include a mask to include an undefined area incorporated into the circuit pattern to leave a critical structure of the circuit pattern undefined. Several embodiments include a photolithography system including an exposure tool, a mask, a source of real-time configurable imaging, and addressing circuitry.

Claims

1. A lithography system, comprising:

an exposure tool to expose a wafer surface to a first beam via a mask, wherein the mask filters the first beam to project a circuit pattern, the circuit pattern comprising an undefined area designed for a circuit structure to complete;

a source of real-time configurable imaging to filter a second beam with a pattern defined by the circuit structure, to project the circuit structure onto a portion of the wafer surface that is associated with the undefined area; and

addressing circuitry to configure the source of real-time configurable imaging with the pattern based upon the circuit structure.

2. The lithography system of claim 1, further comprising a second exposure tool to generate the second beam.

3. The lithography system of claim 1, wherein the source of real-time configurable imaging comprises an array of mirrors adaptable to reflect the second beam toward the wafer surface to create the circuit structure.

4. The lithography system of claim 1, wherein the circuit structure completes a critical circuit of the circuit pattern.

5. The lithography system of claim 1, wherein the source of real-time configurable imaging comprises an optical medium across which an electric potential is applied to create opaque and translucent areas to filter exposure of the wafer surface by the second beam, wherein the optical medium comprises an optical medium selected from an optical medium group comprising a liquid optical medium and a solid optical medium.

6. The lithography system of claim 1, wherein the exposure tool is to direct the beam onto the wafer surface prior to exposing the wafer surface via the second beam.

7. The lithography system of claim 1, wherein the exposure tool is to direct the first exposure beam onto the wafer surface during exposure of the wafer surface via the second exposure beam.

8. The lithography system of claim 1, wherein the source of real-time configurable imaging is to adjust the first and second portions of the second exposure beam to expose the wafer in conjunction with exposure of the wafer by the first exposure beam through the mask via a scanner.

9. The lithography system of claim 1, wherein the source of real-time configurable imaging is to adjust the first and second portions of the second exposure beam to expose the wafer in conjunction with exposure of the wafer by the first exposure beam through the mask via a step-and-scan system.

10. The lithography system of claim 1, wherein the source of real-time configurable imaging is to adjust the first and second portions of the second exposure beam between exposures of the wafer to define a distinct circuit structure in another undefined area of a different exposure field on the wafer.

11. The lithography system of claim 1, wherein the source of real-time configurable imaging is to adjust the first and second portions of the second exposure beam to connect circuits in the circuit pattern defined via exposure through the mask by the first exposure beam.

12. The lithography system of claim 1, wherein the addressing circuitry is to configure the source of real-time configurable imaging to adjust the first and second portions of the second exposure beam to disconnect circuits in the circuit pattern defined via exposure through the mask by the first exposure beam.

13. The lithography system of claim 1, wherein the addressing circuitry is to configure the source of real-time configurable imaging to adjust the first and second portions of the second exposure beam in response to a design decision at the time of manufacture to connect or disconnect missing links within the circuit pattern defined via exposure through the mask by the first exposure beam.

14. The lithography system of claim 1, wherein the addressing circuitry is to configure the source of real-time configurable imaging to adjust the first and second portions of the second exposure beam to connect or disconnect links for the circuit pattern defined via exposure through the mask by the first exposure beam, wherein the circuit pattern resides on another layer of the wafer.