Tamper respondent system

• US 7,787,256 B2
• Filed: 08/10/2007
• Issued: 08/31/2010
• Est. Priority Date: 08/10/2007
• Status: Active Grant

• Current Assignee: W. L. Gore & Associates (W.L. Gore & Associates)
• Original Assignee: Gore Enterprise Holdings Incorporated
• Inventors: Wylie, Harold, Chan, Karl, Lewis, Brent, Murray, Dale
• Primary Examiner(s): Dinh; Tuan T
• Assistant Examiner(s): Semenenko; Yuriy
• Application Number:
  US11/836,870
• Publication Number:
  US 20090040735A1
• Time in Patent Office: 1,117 Days
• Field of Search: 361/760, 361/792, 174/250, 174/258, 174/520, 257788-790
• US Class Current: 361/760
• CPC Class Codes: G06F 21/87 by means of encapsulation, e.g. for integrated circuits
• CPC Class Codes: G08B 13/128 the housing being an electronic circuit unit, e.g. memory or CPU chip protecting computer components in secure or tamper resistant housings G06F21/86; protecting computer input devices, e.g. keyboards G06F21/83
• CPC Class Codes: H01L 23/573 using passive means
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10T 29/49146 with encapsulating, e.g., potting, etc.

Abstract

A tamper respondent system having: a physical volume containing an electronic device to be protected; an at least partially conductive surface proximate to the electronic device; and a tamper respondent sensor over the electronic device (the sensor comprising: a flexible, dielectric substrate; conductive traces on the substrate; a porous insulating layer having pores over the conductive traces; and adhesive within said pores of said porous insulating layer), wherein the adhesive is in contact with both the substrate and the at least partially conductive surface through the porous insulating layer.

Claims

1. A tamper respondent system comprising:

(a) an article to be protected;

(b) a surface proximate to said article;

(c) a tamper respondent sensor between said article and said surface, said sensor comprising;

i. a flexible, dielectric substrate;

ii. conductive traces on said substrate; and

iii. a porous insulating layer having pores over said conductive traces;

(d) an adhesive comprising a combination of epoxy and a pressure sensitive adhesive within said pores of said porous insulating layer,

(e) wherein said adhesive is in contact with both said substrate and said surface through said porous insulating layer.

2. A tamper respondent system as defined in claim 1 wherein said surface is an at least partially conductive surface.

3. A tamper respondent system as defined in claim 2 wherein said at least partially conductive surface is bonded to said tamper respondent sensor by said adhesive.

4. A tamper respondent system as defined in claim 1 wherein said flexible, dielectric substrate comprises polyethyleneterephthalate (“

PET”

).

5. A tamper respondent system as defined in claim 1 wherein said porous insulating layer comprises polyester.

6. A tamper respondent system as defined in claim 1 wherein said adhesive comprises epoxy.

7. A tamper respondent system as defined in claim 1 wherein said article comprises a Personal Computer Memory Card International Association (“

PCMCIA”

) card.

8. A tamper respondent system as defined in claim 1 wherein said surface comprises part of an enclosure chassis.

9. A tamper respondent system as defined in claim 1 wherein said surface comprises part of a chassis.