Integrated circuit embedded with non-volatile multiple-time programmable memory having variable coupling

• US 7,787,295 B2
• Filed: 11/14/2008
• Issued: 08/31/2010
• Est. Priority Date: 11/14/2007
• Status: Expired due to Fees

• Current Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Original Assignee: Jonker LLC
• Inventors: Liu, David, Gross, John Nicholas
• Primary Examiner(s): Nguyen, Tan T.
• Application Number:
  US12/271,695
• Publication Number:
  US 20090122605A1
• Time in Patent Office: 655 Days
• Field of Search: 365/185.01, 365/185.08
• US Class Current: 365/185.03
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7887 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence
• CPC Class Codes: H10B 20/25 One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/47 with a floating-gate layer also being used as part of the peripheral transistor
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A multi-programmable non-volatile device is operated with a floating gate that functions as a FET gate that overlaps a portion of a source/drain region and allows for variable coupling through geometry and/or biasing conditions. This allows a programming voltage for the device to be imparted to the floating gate through variable capacitive coupling, thus changing the state of the device. The invention can be used in environments such as data encryption, reference trimming, manufacturing ID, security ID, and many other applications.

Claims

1. A programmable multi-state non-volatile device situated on a substrate comprising:

a floating gate;

wherein said floating gate is comprised of a material that is also used as a gate for a transistor device also situated on the substrate and associated with a logic gate and/or a volatile memory;

a source region; and

a drain region; and

an n-channel coupling said source region and said drain region;

wherein the drain region overlaps a sufficient portion of said gate such that a programming voltage for the device applied to said drain can be imparted to said floating gate through areal capacitive coupling;

further wherein the device is adapted so that more than one bit of information can be stored by said programming voltage.

2. The programmable device of claim 1 wherein the device is adapted such that during a read operation only a portion of said drain region receives a read voltage.

3. The programmable device of claim 1 wherein the device is adapted such that a portion or all of said drain region can be biased during a program operation to vary an amount of information stored in the device.

4. The programmable device of claim 1 wherein said floating gate can be erased.

5. The programmable device of claim 4 wherein said device can be re-programmed.

6. The programmable device of claim 4 wherein said floating gate is eraseable by an erase voltage applied to said source region.

7. The programmable device of claim 1 wherein said device is part of a programmable array embedded with separate logic circuits and/or memory circuits in an integrated circuit.

8. The programmable device of claim 7 wherein said device is associated with one of the following:

a data encryption circuit;

a reference trimming circuit;

a manufacturing ID; and

/or a security ID.

9. The programmable device of claim 1, wherein said capacitive coupling takes place in a first trench situated in the substrate.

10. The programmable device of claim 9, wherein a set of second trenches in said substrate are used as embedded DRAM.

11. The programmable device of claim 1, further including a second programmable device coupled in a paired latch arrangement such a datum and its compliment are stored in said paired latch.

12. The programmable device of claim 1, wherein the device is adapted to be read by a bias voltage applied to said drain region which is adjusted with time to determine a threshold voltage of said floating gate.

13. The programmable device of claim 1, wherein the device is programmed to a multi-level state by a variable programming voltage.

14. A multi-level programmable device situated on a substrate comprising:

a floating gate;

said floating gate being comprised of a material that includes impurities acting as charge storage sites and is also used as an insulating layer for other non-programmable devices situated on the substrate;

a source region; and

a drain region comprised of a first drain region and a second drain region; and

wherein the drain region overlaps a sufficient portion of said gate such that a programming voltage for the device applied to said drain can be imparted to said floating gate through areal capacitive coupling;

further wherein the device is adapted so that multiple bits of data can be written by said programming voltage.

15. The multi-level programmable device of claim 14 wherein said first drain region and a second drain region have different amounts of areal overlap with said gate.

16. The multi-level programmable device of claim 14 wherein said first drain region has an amount of areal overlap with said gate which is a multiple of that of said second drain region with said gate.

17. The multi-level programmable device of claim 14 wherein a read signal is only applied to one of said first drain region and said second drain region to decode said multiple bits of data.

18. The multi-level programmable device of claim 14 wherein a read signal voltage value is adjusted over time to decode said multiple bits of data.

19. The multi-level programmable device of claim 14 wherein the device is adapted to store an odd number of bits based on an areal coupling of:

1) said first drain region alone;

     2) said second drain region alone;

or

     3) both or neither of said first or second drain regions.

20. The multi-level programmable device of claim 14, wherein said areal capacitive coupling takes place over a C-shaped area.

21. A multi-level one-time programmable (MOTP) device situated on a substrate comprising:

a floating gate;

wherein said floating gate is comprised of a material that is also shared by an interconnect and/or another gate for a transistor device also situated on the substrate and associated with a logic gate and/or a volatile memory;

a source region; and

a drain region overlapping a portion of said floating gate, and said drain region including at least a first drain region and a second selectable drain region;

wherein a variable areal capacitive coupling between said drain region and said floating gate can be effectuated by one or more selection signals applied to said first drain region and said second drain region respectively;

wherein said variable capacitive coupling causes a variable amount of channel hot electrons from said first drain region and from said second drain region to permanently alter a threshold value of said floating gate and store multi-bit data in the OTP device.

22. The MOTP device of claim 21 wherein said first drain region and a second drain region have different amounts of areal overlap with said gate.

23. The MOTP device of claim 21 wherein said first drain region has an amount of areal overlap with said gate which is a multiple of that of said second drain region with said gate.

24. The MOTP device of claim 21 wherein a read signal is only applied to one of said first drain region and said second drain region to decode said multiple bits of data.

25. The MOTP device of claim 21 wherein a read signal voltage value is adjusted over time to decode said multiple bits of data.

26. The MOTP device of claim 21 wherein the device is adapted to store an odd number of bits based on an areal coupling of:

1) said first drain region alone;

     2) said second drain region alone;

or

     3) both or neither of said first or second drain regions.

27. The multi-level programmable device of claim 21, wherein said areal capacitive coupling takes place over a C-shaped area.

28. A multi-level programmable memory device with a gate, an n-type impurity source and an n-type impurity drain on a silicon substrate comprising:

an n-type channel; and

wherein the n-type impurity drain overlaps a sufficient portion of said gate such that a variable programming voltage applied to said n-type impurity drain can be imparted to said gate through areal capacitive coupling and cause a multi-level logic state to be stored in the device;

said gate being adapted to function as a floating gate so that the device has a multi-level programmed state defined by an amount of charge stored on said gate by said variable programming voltage;

further wherein said charge on said floating gate can be erased so as to permit the device to be re-programmed.

29. A multi-level one-time programmable (MOTP) memory cell with a gate, an n-type impurity source and an n-type impurity drain on a silicon substrate comprising:

an n-type channel; and

wherein the n-type impurity drain is adapted to overlap a variable portion of said gate such that a voltage applied to said n-type impurity drain can be imparted to said gate through areal capacitive coupling;

said gate being adapted so that the MOPT cell has a programmed state defined by a charge state of said gate, which charge state corresponds to a plurality of bits of data.

30. The MOTP memory cell of claim 29 wherein said variable portion of said gate overlaps a first area of a first drain region and overlaps a second different sized area of a second drain region within said n-type impurity drain for the cell.

31. The MOTP memory cell of claim 30 wherein a read signal is only applied to one of said first drain region and said second drain region to decode said multiple bits of data.

32. The MOTP memory cell of claim 30 wherein the device is adapted to store an odd number of bits based on an areal coupling of:

1) said first drain region alone;

     2) said second drain region alone;

or

     3) both or neither of said first or second drain regions.

33. The MOTP memory cell of claim 29 wherein a read signal voltage value is adjusted over time to decode said multiple bits of data.

34. The MOTP memory cell of claim 29, wherein said areal capacitive coupling takes place over a C-shaped area.

35. A method of forming a multi-level non-volatile programmable memory device situated on a substrate comprising:

forming a gate for non-volatile programmable memory device from a first layer;

wherein said first layer is shared by the non-volatile programmable memory device and at least one other device also situated on the substrate and associated with a logic gate and/or a volatile memory;

forming a drain region comprised of a first drain region and at least one separate second drain region; and

capacitively coupling said gate with said drain region by overlapping an areal portion of said gate with both said first drain region and said at least one second drain;

wherein the multi-level non-volatile memory device is adapted so that more than one bit of information can be stored in response to a programming voltage.

36. The method of claim 35 wherein the device is adapted such that during a read operation only a portion of said drain region receives a read voltage.

37. The method of claim 35 wherein the device is adapted such that a portion or all of said drain region can be biased during a program operation to vary an amount of information stored in the device.

38. The method of claim 35, wherein the device is adapted wherein the device is adapted to be read by a bias voltage applied to said drain region which is adjusted with time to determine a threshold voltage of said floating gate.

39. A method of operating a multi-level one-time programmable (MOTP) cell situated on a substrate comprising:

providing a floating gate;

wherein said floating gate is comprised of a material that is also shared by an interconnect and/or another gate for a transistor device also situated on the substrate and associated with a logic gate and/or a volatile memory;

providing a source region; and

providing a drain region overlapping a variable portion of said floating gate and capacitively coupled thereto;

wherein an amount of capacitive coupling can be adjusted based on altering a number of N (N>

1) separate drain regions selected to overlap said floating gate and/or by altering a programming voltage level;

setting a threshold of said floating gate based on a current of channel hot electrons;

wherein said threshold can be set to more than two (2) separate distinguishable states to effectuate a multi-level storage cell.

40. The method of claim 39, wherein N=2 and said threshold of said floating gate can be set to one of four (4) different values.

41. The method of claim 39, wherein N=2 and said threshold of said floating gate can be set to one of three (3) different values.

42. The method of claim 39, wherein N=3 and said threshold of said floating gate can be set to one of eight (8) different values.

43. The method of claim 39, wherein N=2 and said threshold of said floating gate can be set to one of more than 2 but less than 8 different values.

44. The method of claim 39, wherein said threshold is determined by a read voltage applied to one or more of said N separate drain regions.

45. The method of claim 44, wherein said read voltage is controlled to have a range of values which vary in time corresponding to threshold states of said floating gate.

46. A method of operating a multi-level non-volatile programmable (MNVP) device situated on a substrate comprising:

providing a floating gate, which floating gate is comprised of a layer and material that is shared by gates of at least some other non-MNVP devices on said substrate;

programming the MNVP device to a first state with channel hot electrons that alter a voltage threshold of a floating gate;

wherein said channel hot electrons are provided by a variable number of drain regions which can be coupled to said floating gate and effectuate a multi-bit logic state for said first state;

reading the first state in the MNVP device using a bias current to detect said voltage threshold; and

erasing the MNVP device with band-band tunneling hot hole injection.