Integrated circuit embedded with non-volatile multiple-time programmable memory having variable coupling
First Claim
Patent Images
1. A programmable multi-state non-volatile device situated on a substrate comprising:
- a floating gate;
wherein said floating gate is comprised of a material that is also used as a gate for a transistor device also situated on the substrate and associated with a logic gate and/or a volatile memory;
a source region; and
a drain region; and
an n-channel coupling said source region and said drain region;
wherein the drain region overlaps a sufficient portion of said gate such that a programming voltage for the device applied to said drain can be imparted to said floating gate through areal capacitive coupling;
further wherein the device is adapted so that more than one bit of information can be stored by said programming voltage.
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Abstract
A multi-programmable non-volatile device is operated with a floating gate that functions as a FET gate that overlaps a portion of a source/drain region and allows for variable coupling through geometry and/or biasing conditions. This allows a programming voltage for the device to be imparted to the floating gate through variable capacitive coupling, thus changing the state of the device. The invention can be used in environments such as data encryption, reference trimming, manufacturing ID, security ID, and many other applications.
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Citations
46 Claims
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1. A programmable multi-state non-volatile device situated on a substrate comprising:
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a floating gate; wherein said floating gate is comprised of a material that is also used as a gate for a transistor device also situated on the substrate and associated with a logic gate and/or a volatile memory; a source region; and a drain region; and an n-channel coupling said source region and said drain region; wherein the drain region overlaps a sufficient portion of said gate such that a programming voltage for the device applied to said drain can be imparted to said floating gate through areal capacitive coupling; further wherein the device is adapted so that more than one bit of information can be stored by said programming voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A multi-level programmable device situated on a substrate comprising:
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a floating gate;
said floating gate being comprised of a material that includes impurities acting as charge storage sites and is also used as an insulating layer for other non-programmable devices situated on the substrate;a source region; and a drain region comprised of a first drain region and a second drain region; and wherein the drain region overlaps a sufficient portion of said gate such that a programming voltage for the device applied to said drain can be imparted to said floating gate through areal capacitive coupling; further wherein the device is adapted so that multiple bits of data can be written by said programming voltage. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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21. A multi-level one-time programmable (MOTP) device situated on a substrate comprising:
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a floating gate; wherein said floating gate is comprised of a material that is also shared by an interconnect and/or another gate for a transistor device also situated on the substrate and associated with a logic gate and/or a volatile memory; a source region; and a drain region overlapping a portion of said floating gate, and said drain region including at least a first drain region and a second selectable drain region; wherein a variable areal capacitive coupling between said drain region and said floating gate can be effectuated by one or more selection signals applied to said first drain region and said second drain region respectively; wherein said variable capacitive coupling causes a variable amount of channel hot electrons from said first drain region and from said second drain region to permanently alter a threshold value of said floating gate and store multi-bit data in the OTP device. - View Dependent Claims (22, 23, 24, 25, 26, 27)
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28. A multi-level programmable memory device with a gate, an n-type impurity source and an n-type impurity drain on a silicon substrate comprising:
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an n-type channel; and wherein the n-type impurity drain overlaps a sufficient portion of said gate such that a variable programming voltage applied to said n-type impurity drain can be imparted to said gate through areal capacitive coupling and cause a multi-level logic state to be stored in the device; said gate being adapted to function as a floating gate so that the device has a multi-level programmed state defined by an amount of charge stored on said gate by said variable programming voltage; further wherein said charge on said floating gate can be erased so as to permit the device to be re-programmed.
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29. A multi-level one-time programmable (MOTP) memory cell with a gate, an n-type impurity source and an n-type impurity drain on a silicon substrate comprising:
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an n-type channel; and wherein the n-type impurity drain is adapted to overlap a variable portion of said gate such that a voltage applied to said n-type impurity drain can be imparted to said gate through areal capacitive coupling; said gate being adapted so that the MOPT cell has a programmed state defined by a charge state of said gate, which charge state corresponds to a plurality of bits of data. - View Dependent Claims (30, 31, 32, 33, 34)
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35. A method of forming a multi-level non-volatile programmable memory device situated on a substrate comprising:
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forming a gate for non-volatile programmable memory device from a first layer; wherein said first layer is shared by the non-volatile programmable memory device and at least one other device also situated on the substrate and associated with a logic gate and/or a volatile memory; forming a drain region comprised of a first drain region and at least one separate second drain region; and capacitively coupling said gate with said drain region by overlapping an areal portion of said gate with both said first drain region and said at least one second drain; wherein the multi-level non-volatile memory device is adapted so that more than one bit of information can be stored in response to a programming voltage. - View Dependent Claims (36, 37, 38)
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39. A method of operating a multi-level one-time programmable (MOTP) cell situated on a substrate comprising:
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providing a floating gate; wherein said floating gate is comprised of a material that is also shared by an interconnect and/or another gate for a transistor device also situated on the substrate and associated with a logic gate and/or a volatile memory; providing a source region; and providing a drain region overlapping a variable portion of said floating gate and capacitively coupled thereto; wherein an amount of capacitive coupling can be adjusted based on altering a number of N (N>
1) separate drain regions selected to overlap said floating gate and/or by altering a programming voltage level;setting a threshold of said floating gate based on a current of channel hot electrons; wherein said threshold can be set to more than two (2) separate distinguishable states to effectuate a multi-level storage cell. - View Dependent Claims (40, 41, 42, 43, 44, 45)
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46. A method of operating a multi-level non-volatile programmable (MNVP) device situated on a substrate comprising:
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providing a floating gate, which floating gate is comprised of a layer and material that is shared by gates of at least some other non-MNVP devices on said substrate; programming the MNVP device to a first state with channel hot electrons that alter a voltage threshold of a floating gate; wherein said channel hot electrons are provided by a variable number of drain regions which can be coupled to said floating gate and effectuate a multi-bit logic state for said first state; reading the first state in the MNVP device using a bias current to detect said voltage threshold; and erasing the MNVP device with band-band tunneling hot hole injection.
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Specification