Nonvolatile semiconductor memories for preventing read disturbance and reading methods thereof

• US 7,787,306 B2
• Filed: 07/14/2008
• Issued: 08/31/2010
• Est. Priority Date: 07/13/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Chang-Sub, Lim, Young-Ho, Park, Jung-Hoon, Park, Ki-Tae, Lee, Sung-Soo
• Primary Examiner(s): Lam; David
• Application Number:
  US12/172,904
• Publication Number:
  US 20090052257A1
• Time in Patent Office: 778 Days
• Field of Search: 365/185.23, 36518517-18518, 365/185.21, 365/185.03, 365/185.33, 365/230.06
• US Class Current: 365/185.23
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written

Abstract

A method of reading a flash memory device can include driving a selected word line by applying a selection voltage thereto and driving unselected word lines by applying a first voltage thereto, driving the unselected word lines and first and second selection lines by applying a second voltage that is higher than the first voltage thereto, and reading data from a memory cell that is coupled to the selected word line.

Claims

1. A method of reading a flash memory device, comprising:

(a) driving a selected word line by applying a selection voltage thereto, and driving unselected word lines and first and second selection lines by applying a second voltage thereto;

(b) driving the second selection line by applying a ground voltage thereto;

(c) driving the second selection line by applying the second voltage thereto; and

(d) reading data from a memory cell that is coupled to the selected word line.

2. The method of claim 1, further comprising discharging a channel voltage generated in a memory cell string into a bit line or a common source line during (a).

3. The method of claim 1, further comprising driving the selected word line by applying the selection voltage thereto and driving the unselected word lines and the first selection line by applying the second voltage thereto during (b).

4. The method of claim 1, further comprising precharging a bit line to a predetermined voltage level during (b).

5. The method of claim 1, further comprising driving the selected word line by applying the selection voltage thereto and driving the unselected word lines and the first selection line by applying the second voltage thereto during (c).

6. The method of claim 1, further comprising driving a common source line by applying a ground voltage thereto.