Network interface controller with receive side scaling and quality of service

• US 7,787,453 B2
• Filed: 08/02/2007
• Issued: 08/31/2010
• Est. Priority Date: 08/03/2006
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Chou, Henry, Hwang, Andrew, Tran, Thanh
• Primary Examiner(s): Cho; Hong
• Assistant Examiner(s): Foud; Hicham B.
• Application Number:
  US11/882,550
• Publication Number:
  US 20080034101A1
• Time in Patent Office: 1,125 Days
• Field of Search: None
• US Class Current: 370/389
• CPC Class Codes: H04L 45/302 Route determination based on requested QoS
• CPC Class Codes: H04L 45/745 Address table lookup; Address filtering
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 69/161 Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields

Abstract

The present invention is directed to methods and systems for scaling receive protocol processing by allowing the network load from a network adapter to be balanced across multiple CPUs based on RSS and/or QoS traffic classification techniques.

Claims

1. A method for delivering data input to a central processing unit (CPU) in a multi-CPU computer system, the method comprising:

(a) receiving a data packet and a resolution control signal;

(b) parsing a portion of the data packet comprising;

(i) applying a function to the portion of the data packet to generate a first CPU queue identifier and a first valid signal; and

(ii) applying user defined rules to the portion of the data packet to generate a second CPU queue identifier and a second valid signal;

(c) generating a global CPU queue identifier based on the first and second CPU queue identifiers, first and second valid signals, and the resolution control signal; and

(d) routing the data packet to a CPU defined by the global CPU queue identifier.

2. The method of claim 1, wherein the first CPU queue identifier and first valid signal are generated in parallel with the second CPU queue identifier and second valid signal.

3. The method of claim 1, wherein step (b)(i) further comprises applying a Receive Side Scaling (RSS) function to the portion of the data packet to generate a RSS CPU queue identifier and a RSS valid signal.

4. The method of claim 1, wherein step (b)(ii) further comprises applying Quality of Service (QoS) rules to the portion of the data packet to generate a QoS CPU queue identifier and a QoS valid signal.

5. The method of claim 1, wherein the receiving step further comprises:

(i) receiving a first enable signal; and

(ii) receiving a second enable signal;

wherein the parsing step is controlled by the first and second enable signals.

6. A network interface controller system, comprising:

a receive side scaling (RSS) engine wherein the RSS engine receives a plurality of data packets and produces an RSS CPU queue identifier and a first valid signal;

a quality of service (QoS) engine wherein the QoS engine receives a plurality of inputs and produces a QoS CPU queue identifier and a second valid signal; and

a resolution logic module coupled to both the RSS engine and the QoS engine, wherein the resolution logic module receives the RSS CPU queue identifier, the QoS CPU queue identifier, the first and second valid signals, and a resolution control signal, and produces an output CPU queue identifier that identifies a CPU to receive at least a portion of the plurality of data packets.

7. The network interface controller system of claim 6, wherein the RSS engine comprises hash logic.

8. The network interface controller system of claim 6, further comprising user input means for providing rules to the QoS engine.

9. The network interface controller system of claim 6, further comprising user input means for enabling one or more of the RSS engine and QoS engine and means for receiving the resolution control signal.

10. The network interface controller system of claim 6, wherein the data packets each comprise data packet headers and data, wherein the data packet headers are formatted according to one or more of the TCP, IPv4, IPv6, Ethernet and Ethernet LAN standards.