System and method for adjusting offset compensation applied to a signal

• US 7,787,534 B2
• Filed: 05/24/2007
• Issued: 08/31/2010
• Est. Priority Date: 05/30/2006
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Hidaka, Yasuo
• Primary Examiner(s): Ahn; Sam K
• Application Number:
  US11/753,093
• Publication Number:
  US 20070297209A1
• Time in Patent Office: 1,195 Days
• Field of Search: 375229-236, 333/18, 333/28.R, 708/300, 708/322, 708/323, 379/340, 379/398
• US Class Current: 375/229
• CPC Class Codes: G01D 21/00 Measuring or testing not otherwise provided for
• CPC Class Codes: H04L 25/03343 Arrangements at the transmitter end
• CPC Class Codes: H04L 25/03885 adaptive
• CPC Class Codes: H04L 25/068 by sampling faster than the nominal bit rate

Abstract

In one embodiment of the present invention, a method for adjusting a signal includes receiving an input data signal. The method also includes applying an offset compensation to the input data signal to generate an output signal. The method further includes, using a clock signal, sampling the output signal to generate a plurality of data values and boundary values, each value comprising either a high value or a low value based on the sampling of the output signal. The method also includes detecting a transition in value between two successive data values and determining a sampled boundary value between the two successive data values. The method further includes, based at least on the high or low value of the boundary value, adjusting the offset compensation applied to the input data signal.

Claims

1. A method for adjusting a signal at a receiver of a digital signal transmission system, comprising:

receiving an input data signal at a receiver of a digital signal transmission system;

using the receiver, applying an offset compensation to the input data signal to generate an output signal;

using a clock signal at the receiver, sampling the output signal to generate a plurality of data values and boundary values, each data value and each boundary value comprising either a high value or a low value based on the sampling of the output signal;

detecting, by the receiver, a transition in value between two successive data values and determining a sampled boundary value between the two successive data values; and

based only on the high or low value of the boundary value, adjusting by the receiver the offset compensation applied to the input data signal.

2. The method of claim 1, wherein the offset compensation applied to the input data signal is made negative when the boundary value is high.

3. The method of claim 1, wherein the offset compensation applied to the input data signal is made positive when the boundary value is low.

4. The method of claim 1, wherein the clock signal is associated with the output signal.

5. The method of claim 1, wherein the input data signal is not a test signal.

6. A receiver, comprising:

an input port configured to receive an input data signal;

an amplifier configured to apply an offset compensation to the input data signal to generate an output signal;

a sampler configured to;

receive the output signal and a clock signal; and

using the clock signal, sample the output signal to generate a plurality of data values and boundary values, each data value and each boundary value comprising either a high value or a low value based on the sampling of the output signal; and

a controller configured to;

detect a transition in value between two successive data values and determine a sampled boundary value between the two successive data values; and

adjust the offset compensation applied by the amplifier to the input data signal based only on the high or low value of the boundary value.

7. The receiver of claim 6, wherein the offset compensation applied to the input data signal is made negative when the boundary value is high.

8. The receiver of claim 6, wherein the offset compensation applied to the input data signal is made positive when the boundary value is low.

9. The receiver of claim 6, wherein the clock signal is associated with the output signal.

10. The receiver of claim 6, wherein the input data signal is not a test signal.