Sensor-network processors using event-driven architecture

• US 7,788,332 B2
• Filed: 05/06/2005
• Issued: 08/31/2010
• Est. Priority Date: 05/06/2004
• Status: Active Grant

• Current Assignee: Cornell Research Foundation Incorporated (Cornell University)
• Original Assignee: Cornell Research Foundation Incorporated (Cornell University)
• Inventors: Kelly, Clint, Manohar, Rajit
• Primary Examiner(s): Dharia; Rupal D
• Assistant Examiner(s): Fan; Hua
• Application Number:
  US11/123,234
• Publication Number:
  US 20060075210A1
• Time in Patent Office: 1,943 Days
• Field of Search: 709206-207, 713/502, 711/206
• US Class Current: 709/207
• CPC Class Codes: G01D 21/00 Measuring or testing not otherwise provided for
• CPC Class Codes: H04W 24/00 Supervisory, monitoring or testing arrangements
• CPC Class Codes: H04W 52/0216 using a pre-established activity schedule, e.g. traffic indication frame
• CPC Class Codes: H04W 52/0219 where the power saving management affects multiple terminals
• CPC Class Codes: H04W 80/00 Wireless network protocols or protocol adaptations to wireless operation
• CPC Class Codes: H04W 84/18 Self-organising networks, e.g. ad-hoc networks or sensor networks

Abstract

Event-driven processor architectures are particularly suited for use in multiple sensor node networks and simulators of such networks. A first variation of the processor is particularly suited for use in a sensor node in a wireless sensor network. Through use of the event-driven architecture and special message and timing coprocessors, this embodiment of the invention is optimized for low energy requirements and data monitoring operations in sensor networks. A second embodiment of the invention includes modifications necessary for use of the processor in a network simulation protocol.

Claims

1. An event-driven processor for executing tasks in response to the occurrence of one or more events, said processor comprising:

a processor core that includes;

a memory;

at least one execution unit;

an event queue for storing one or more event tokens, each of which contains event identification information that indicates an event that has occurred which requires that a corresponding task is to be executed by said execution unit and a location in said memory where one or more instructions corresponding to the task to be executed by said execution unit is located;

a fetch for sequentially processing each of said event tokens in said event queue by carrying out the processing steps of;

retrieving a first of said event tokens from said queue;

employing said event identification information to locate and fetch one or more instructions from said memory for execution by said execution unit, said instructions corresponding to the task to be executed;

atomically delivering said instructions to said execution unit for execution until a done instruction is fetched from said memory which indicates that all of the instructions for said task have been fetched and delivered to said execution unit; and

when said done instruction is fetched, repeating said processing steps for a next event token if present in said queue, but if said queue is empty, ceasing further fetching of instructions from said memory until another event token is detected in said event queue by said fetch;

—

a message coprocessor for generating external event tokens in response to communications received from one or more external devices and placing said external event tokens in said event queue for processing by said processor core; and

a timer coprocessor for generating an internal event token when a timeout occurs and placing said internal event token in said event queue to cause said fetch to retrieve instructions corresponding to said internal event token from said memory and deliver said instructions to said execution unit for execution;

whereby, said execution unit periodically transitions from an idle state to an active state even when no external event tokens have been placed into said event queue by said message coprocessor.

2. The processor of claim 1, wherein said timer coprocessor includes a plurality of said timers, each of which can be set to time out at after expiration of a predetermined interval.

3. The processor of claim 1, wherein said processor is configured to operate in a polling mode by sending a signal periodically from said execution unit to said message coprocessor which causes said message coprocessor to request data from at least one external device and upon receipt of data from said at least one external device, place a corresponding event token in said event queue.

4. The processor of claim 1, wherein said processor includes a plurality of said execution units and said processor further comprises a plurality of registers;

a high speed bus interconnecting said registers to ones of said execution units that are frequently used and a slow speed bus interconnecting said registers to other ones of said execution units through said high speed bus.

5. A system comprising a plurality of the processors of claim 1 which are formed in a network on a semiconductor chip.

6. The processor of claim 1, wherein said processor is an asynchronous, clockless processor which automatically transitions to a low power sleep state when all event tokens in said queue have been processed and transitions out of said sleep state when another event token is placed in said event queue.

7. The processor of claim 1, wherein said processor forms part of a sensor-network processing node in a network of said nodes and said node includes one or more sensors for measuring one or more parameters and communicating said measurements to said processor;

and a radio transceiver for enabling said node to communicate with other nodes in said network.

8. An event-driven method for managing events with a processor that includes a memory, at least one execution unit, an event queue, a fetch, a message coprocessor and a timer coprocessor, said method comprising the steps of:

generating one or more external event tokens with said message coprocessor, each of which contains event identification information that indicates an external event that has occurred which requires that a corresponding task is to be executed by said execution unit and a location in said memory where one or more instructions corresponding to the task to be executed by said execution unit is located;

generating one or more internal event tokens with said timer coprocessor, each of which contains event identification information that indicates an internal timeout event that has occurred which requires that a corresponding task is to be executed by said execution unit and a location in said memory where one or more instructions corresponding to the task to be executed by said execution unit is located;

placing each of said event tokens in said event queue; and

in response to detection by said fetch that at least one token is present in said event queue, said fetch carrying out the steps of;

retrieving a first of said event tokens from said event queue;

employing said event identification information to locate and fetch one or more instructions from said memory for execution by said execution unit, said instructions corresponding to the task to be executed;

atomically delivering said instructions to said execution unit for execution until a done instruction is fetched from said memory which indicates that said execution unit is done executing all of the instructions for said task; and

when said done instruction is fetched, repeating said processing steps for a next event token if present in said queue, but if said queue is empty, ceasing further fetching of instructions from said memory until another event token is detected in said event queue by said fetch.

9. The method of claim 8, wherein when said fetch retrieves an internal event token from said event queue that has been placed in said event queue by said timer coprocessor and requests polling of said one or more external devices by said processor, said fetch retrieves one or more instructions from said memory which, when sequentially delivered to said one or more execution units for execution, cause said one or more execution units to send a command to said message coprocessor to obtain information from said one or more external devices and when information is obtained from said one or more external devices, said message coprocessor generates one or more external event tokens and places them into said event queue for processing by said one or more execution units.

10. The method of claim 8, wherein a plurality of said execution units is provided and a register file in said processor communicates with frequently used ones of said execution units via a high speed bus and communicates with other ones of said execution units with a slow speed bus.

11. The method of claim 8, wherein a plurality of said processors are formed in a network on a semiconductor chip and each said processor is configured to carry out the steps of claim 8.

12. The method of claim 11, wherein each of said processors forms part of a corresponding sensor node in said network and each node further includes one or more sensors which send sensor measurement information to said processor and a radio transceiver for communicating with other ones of said processors in said network.

13. The method of claim 8, wherein said processor is an asynchronous, clockless processor which automatically transitions to a low power sleep state when all event tokens in said queue have been processed and transitions out of said sleep state when another event token is placed in said event queue.