Memory controller and method of controlling a memory
First Claim
Patent Images
1. A memory controller configured to interface with a memory to control the memory, the memory controller comprising:
- a control circuit configured to provide a control signal;
an output interface unit; and
a programmable command storage unit coupled to the control circuit and the output interface and configured to store a plurality of commands, receive the control signal, and provide, in response to the control signal, a selected command of the plurality of commands to the output interface unit;
wherein the output interface is configured to provide the selected command to the memory;
wherein the programmable command storage unit is configured to store control information associated with the command and provide the control information to the control circuit;
wherein the control circuit is configured to generate a new control signal based on the control information and to provide the new control signal to the programmable command storage unit to thereby cause the programmable command storage unit to output a new selected command to the output interface unit;
wherein the control information comprises delay count information and the control circuit is configured to control a delay between selected commands output from the programmable command storage unit based on the delay count information.
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Abstract
A memory controller includes a control circuit configured to provide a control signal, an output interface unit, and a command storage unit coupled to the control circuit and the output interface. The command storage unit is configured to store a plurality of commands, receive the control signal, and provide, in response to the control signal, a selected command of the plurality of commands to the output interface unit.
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Citations
30 Claims
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1. A memory controller configured to interface with a memory to control the memory, the memory controller comprising:
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a control circuit configured to provide a control signal; an output interface unit; and a programmable command storage unit coupled to the control circuit and the output interface and configured to store a plurality of commands, receive the control signal, and provide, in response to the control signal, a selected command of the plurality of commands to the output interface unit; wherein the output interface is configured to provide the selected command to the memory; wherein the programmable command storage unit is configured to store control information associated with the command and provide the control information to the control circuit; wherein the control circuit is configured to generate a new control signal based on the control information and to provide the new control signal to the programmable command storage unit to thereby cause the programmable command storage unit to output a new selected command to the output interface unit; wherein the control information comprises delay count information and the control circuit is configured to control a delay between selected commands output from the programmable command storage unit based on the delay count information. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A memory controller configured to interface with a memory to control the memory, the memory controller comprising:
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a first interface; a second interface; a programmable register unit coupled to the first interface and the second interface and configured to receive at least one command via the first interface and store the at least one command; and a control circuit coupled to the programmable register unit and configured to control outputting of a selected command from the programmable register unit to the second interface; wherein the second interface is configured to provide the selected command to the memory; wherein the programmable register unit is configured to store control information associated with the command and provide the control information to the control circuit; wherein the control circuit is configured to generate a new control signal based on the control information and to provide the new control signal to the programmable register unit to thereby cause the programmable register unit to output a new selected command to the second interface; wherein the control information comprises delay count information and the control circuit is configured to control a delay between selected commands output from the programmable register unit based on the delay count information. - View Dependent Claims (11, 12, 13, 14, 15)
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16. A memory controller configured to interface with a memory to control the memory, the memory controller comprising:
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a first interface; a second interface; a programmable first register unit coupled to the first interface and the second interface and configured to store at least one command received via the first interface; and a control circuit coupled to the first register unit and configured to control outputting of a selected command of the at least one command from the first register unit to the second interface; and wherein the programmable first register unit is configured to store control information associated with the command output from the programmable first register unit; wherein the second interface is configured to provide the selected command to the memory; wherein the programmable first register unit is configured to provide the control information to the control circuit when the selected command is output to the second interface; wherein the control information associated with the command which is being output is provided to the control circuit; wherein the outputting of a subsequent new command from the programmable first register unit is controlled by the control circuit based on the control information received from the programmable first register unit; wherein the control information comprises delay count information and the control circuit is configured to control a delay between commands output from the programmable first register unit based on the delay count information. - View Dependent Claims (17, 18, 19, 20, 21)
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22. A memory unit, comprising:
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a memory; a memory interface unit coupled to the memory; and a memory controller coupled to the memory interface unit and comprising; programmable means for storing a plurality of commands; and means for providing a control signal to control outputting of a command from the means for storing a plurality of commands to the memory interface unit; wherein the programmable means includes means for storing control information associated with the command and means for providing the control information to the means for controlling; wherein the means for providing the control signal includes means for generating a new control signal based on the control information and means for providing the new control signal to the programmable means to cause the programmable means to output a new selected command; wherein the control information comprises delay count information and the means for controlling controls a delay between commands output from the programmable means based on the delay count information. - View Dependent Claims (23, 24, 25)
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26. A method of controlling a memory, comprising:
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providing a memory controller coupled to the memory and comprising a programmable command storage unit having stored therein a plurality of commands; retrieving a command of the plurality of commands from the programmable command storage unit; outputting the command from the memory controller to the memory; storing control information associated with the command in the programmable command storage unit, wherein the control information comprises delay count information; providing the control information associated with the command which is being output to a control circuit; outputting a subsequent new command from the programmable command storage unit under control of the control circuit based on the control information received from the programmable command storage unit; and controlling a delay between commands output from the programmable command storage unit based on the delay count information. - View Dependent Claims (27, 28, 29)
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30. A method of controlling a memory, comprising:
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providing a memory controller separate from the memory having a plurality of operation modes and comprising a programmable register unit wherein the memory controller has a plurality of operation modes which are associated with a plurality of different memories or memory interfaces; selecting an operation mode for the memory controller from the plurality of operation modes based on the memory which is to be controlled; storing a plurality of commands in the programmable register unit based on the selected operation mode; storing control information associated with a first command in the programmable register unit, wherein the control information comprises delay count information; outputting the first command from the programmable register unit to the memory; providing the control information to a control circuit; outputting a second command from the programmable register unit under control of the control circuit based on the control information received from the programmable register unit; and controlling a delay between commands output from the programmable register unit based on the delay count information.
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Specification