Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system

• US 7,788,451 B2
• Filed: 02/05/2004
• Issued: 08/31/2010
• Est. Priority Date: 02/05/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Larson, Douglas A., Cronin, Jeffrey J.
• Primary Examiner(s): Thai; Tuan V
• Assistant Examiner(s): Doan; Duc T
• Application Number:
  US10/773,583
• Publication Number:
  US 20050177695A1
• Time in Patent Office: 2,399 Days
• Field of Search: 711/138
• US Class Current: 711/138
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

A memory hub includes first and second link interfaces for coupling to respective data busses, a data path coupled to the first and second link interfaces and through which data is transferred between the first and second link interfaces, and further includes a write bypass circuit coupled to the data path to couple write data on the data path and temporarily store the write data to allow read data to be transferred through the data path while the write data is temporarily stored. A method for writing data to a memory location in a memory system is provided which includes accessing read data in the memory system, providing write data to the memory system, and coupling the write data to a register for temporary storage. The write data is recoupled to the memory bus and written to the memory location following provision of the read data.

Claims

1. A method for executing read and write commands in a memory system having a bidirectional memory bus coupling a controller to a first, second, and third memory hub, the second memory hub being downstream from the first memory hub, and the third memory hub being downstream from the second memory hub, the method comprising:

the controller issuing a read command to access a first memory location in a first memory device coupled to the second memory hub;

after the controller issues the read command and before receiving read data corresponding to the issued read command, the controller issuing a write command to write data to a second memory location in a second memory device coupled to the third memory hub, the controller further providing write data corresponding to the issued write command to the bi-directional memory bus;

retrieving the read data from the first memory location and providing the read data to the bi-directional memory bus;

the controller providing a bypass enable signal to the first memory hub;

in response to receiving the bypass enable signal, the first memory hub storing the write data to allow the read data on the bidirectional memory bus to be coupled to the controller; and

the first memory hub providing the write data to the bidirectional memory bus.

2. The method of claim 1 wherein bypassing the read data on the memory bus comprises decoupling the write data from the memory bus for a time period to avoid data collision on the memory bus.

3. The method of claim 2, further comprising temporarily storing the write data in a bypass buffer during the receipt of the read data.

4. The method of claim 2 wherein providing the write data to the memory bus comprises providing the write data through at least one memory module of the memory system before decoupling the write data from the memory bus.

5. A method for writing data to a memory location in a memory system, the memory system including a controller coupled to a first, second, and third memory hub by a bidirectional memory bus, the second memory hub being located downstream from the first memory hub, the third memory hub being located downstream from the second memory hub, the method comprising:

the controller issuing a read command to a first memory location of a first memory device coupled to the second memory hub;

after the controller issuing the read command and before receiving corresponding read data, the controller issuing a write command to a second memory location of a second memory device coupled to the third memory hub and providing write data corresponding to the issued write command to the bidirectional memory bus;

coupling the read data corresponding to the previously issued read command to the bidirectional memory bus;

the controller providing a bypass enable signal to the first memory hub;

in response to the bypass enable signal, the first memory hub coupling the write data to a register in the memory system for temporary storage of the write data to allow the read data corresponding to the previously issued read command to propagate on the bidirectional data bus;

recoupling the write data stored in the register to the bidirectional memory bus; and

writing the write data to the memory location.

6. The method of claim 5 wherein issuing the read command to the memory system precedes issuing the write command to the memory system.

7. The method of claim 5 further comprising temporarily storing the write data in a bypass buffer during the receipt of the read data.

8. The method of claim 5 wherein providing the write data to the memory bus comprises providing the write data through at least one memory module of the memory system before decoupling the write data from the memory bus.

9. A method for executing memory commands in a memory system having a bidirectional memory bus on which both read and write data can be coupled, the memory system including a controller coupled to a first, second, and third memory hub, the second memory hub being downstream from the first memory hub, the third memory hub being downstream from the second memory hub, the method comprising:

the controller issuing a read command to a first memory location in a first memory device coupled to the second memory hub;

the controller issuing a write command to a second memory location in a second memory device coupled to the third memory hub and providing write data corresponding to the write command to the bidirectional memory bus of the memory system after issuing the read command;

accessing read data from the first memory location, the read data corresponding to the previously issued read command;

coupling the read data corresponding to the previously issued read command to the bidirectional memory bus;

the controller providing a bypass enable signal to the first memory hub;

in response to the bypass enable signal, decoupling the write data in the first memory hub from the bidirectional memory bus preventing a collision between the read data and the write data;

propagating the read data on the bidirectional memory bus through the first memory hub; and

recoupling the write data to the bidirectional memory bus.

10. The method of claim 9 wherein bypassing the read data on the memory bus comprises decoupling the write data from the memory bus for a time period to avoid data collision on the memory bus.

11. The method of claim 10 further comprising temporarily storing the write data in a bypass buffer during the receipt of the read data.

12. The method of claim 10 wherein providing the write data to the memory bus comprises providing the write data through at least one memory module of the memory system before decoupling the write data from the memory bus.

13. A memory system comprising:

a bidirectional memory bus;

a controller coupled to a first, second, and third memory hub, the second memory hub being downstream from the first memory hub, and the third memory hub being downstream from the second memory hub;

the controller coupled to the bidirectional memory bus, wherein the controller is configured to issue a read command to access a first memory location in a first memory device coupled to the second memory hub;

after the controller issues the read command and before receiving read data corresponding to the issued read command, the controller issuing a write command to write data to a second memory location in a second memory device coupled to the third memory hub, the controller further providing write data corresponding to the issued write command to the bi-directional memory bus, the controller further configured to issue a bypass enable signal; and

the first memory hub[coupled to the controller by the bidirectional memory bus, the first memory hub] including a bypass circuit configured to receive the write data from the bidirectional memory bus and to store the write data in response to receiving the bypass enable signal from the controller,

wherein the bypass circuit is configured to store the write data in the first memory hub in response to receiving the bypass enable signal to allow the read data to propagate on the bidirectional memory bus passed the write data in the first memory hub and to prevent a data collision between the read data and the write data on the bidirectional memory bus.

14. The memory system of claim 13 wherein the bypass circuit comprises a register configured to receive and store the write data.